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Differential D27168

AMDGPU: Use SGPR_64 for argument lowerings
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Authored by arsenm on Nov 28 2016, 9:08 AM.

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• tstellarAMD

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arsenm updated this revision to Diff 79412.Nov 28 2016, 9:08 AM

arsenm retitled this revision from to AMDGPU: Use SGPR_64 for argument lowerings.

arsenm updated this object.

arsenm added a subscriber: llvm-commits.

Herald added a reviewer: • tstellarAMD. · View Herald TranscriptNov 28 2016, 9:09 AM

Herald added subscribers: tony-tye, yaxunl, nhaehnle and 2 others. · View Herald Transcript

LGTM.

This revision is now accepted and ready to land.Nov 29 2016, 7:16 AM

r288190

Revision Contents

Path

Size

lib/

Target/

AMDGPU/

SIISelLowering.cpp

14 lines

Diff 79412

lib/Target/AMDGPU/SIISelLowering.cpp

Show First 20 Lines • Show All 811 Lines • ▼ Show 20 Lines	SDValue SITargetLowering::LowerFormalArguments(
if (Info->hasPrivateSegmentBuffer()) {		if (Info->hasPrivateSegmentBuffer()) {
unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);		unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);
MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);		MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);
CCInfo.AllocateReg(PrivateSegmentBufferReg);		CCInfo.AllocateReg(PrivateSegmentBufferReg);
}		}

if (Info->hasDispatchPtr()) {		if (Info->hasDispatchPtr()) {
unsigned DispatchPtrReg = Info->addDispatchPtr(*TRI);		unsigned DispatchPtrReg = Info->addDispatchPtr(*TRI);
MF.addLiveIn(DispatchPtrReg, &AMDGPU::SReg_64RegClass);		MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
CCInfo.AllocateReg(DispatchPtrReg);		CCInfo.AllocateReg(DispatchPtrReg);
}		}

if (Info->hasQueuePtr()) {		if (Info->hasQueuePtr()) {
unsigned QueuePtrReg = Info->addQueuePtr(*TRI);		unsigned QueuePtrReg = Info->addQueuePtr(*TRI);
MF.addLiveIn(QueuePtrReg, &AMDGPU::SReg_64RegClass);		MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
CCInfo.AllocateReg(QueuePtrReg);		CCInfo.AllocateReg(QueuePtrReg);
}		}

if (Info->hasKernargSegmentPtr()) {		if (Info->hasKernargSegmentPtr()) {
unsigned InputPtrReg = Info->addKernargSegmentPtr(*TRI);		unsigned InputPtrReg = Info->addKernargSegmentPtr(*TRI);
MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);		MF.addLiveIn(InputPtrReg, &AMDGPU::SGPR_64RegClass);
CCInfo.AllocateReg(InputPtrReg);		CCInfo.AllocateReg(InputPtrReg);
}		}

if (Info->hasDispatchID()) {		if (Info->hasDispatchID()) {
unsigned DispatchIDReg = Info->addDispatchID(*TRI);		unsigned DispatchIDReg = Info->addDispatchID(*TRI);
MF.addLiveIn(DispatchIDReg, &AMDGPU::SReg_64RegClass);		MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
CCInfo.AllocateReg(DispatchIDReg);		CCInfo.AllocateReg(DispatchIDReg);
}		}

if (Info->hasFlatScratchInit()) {		if (Info->hasFlatScratchInit()) {
unsigned FlatScratchInitReg = Info->addFlatScratchInit(*TRI);		unsigned FlatScratchInitReg = Info->addFlatScratchInit(*TRI);
MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SReg_64RegClass);		MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
CCInfo.AllocateReg(FlatScratchInitReg);		CCInfo.AllocateReg(FlatScratchInitReg);
}		}

if (!AMDGPU::isShader(CallConv))		if (!AMDGPU::isShader(CallConv))
analyzeFormalArgumentsCompute(CCInfo, Ins);		analyzeFormalArgumentsCompute(CCInfo, Ins);
else		else
AnalyzeFormalArguments(CCInfo, Splits);		AnalyzeFormalArguments(CCInfo, Splits);

Show All 38 Lines	for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
}		}
assert(VA.isRegLoc() && "Parameter must be in a register!");		assert(VA.isRegLoc() && "Parameter must be in a register!");

unsigned Reg = VA.getLocReg();		unsigned Reg = VA.getLocReg();

if (VT == MVT::i64) {		if (VT == MVT::i64) {
// For now assume it is a pointer		// For now assume it is a pointer
Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,		Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
&AMDGPU::SReg_64RegClass);		&AMDGPU::SGPR_64RegClass);
Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);		Reg = MF.addLiveIn(Reg, &AMDGPU::SGPR_64RegClass);
SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);		SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
InVals.push_back(Copy);		InVals.push_back(Copy);
continue;		continue;
}		}

const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);		const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);

Reg = MF.addLiveIn(Reg, RC);		Reg = MF.addLiveIn(Reg, RC);
▲ Show 20 Lines • Show All 3,335 Lines • Show Last 20 Lines