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AMDGPU: Fix not setting kill flag on temp reg when spilling
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Authored by arsenm on Nov 23 2016, 10:11 AM.

Reviewers

• tstellarAMD

arsenm retitled this revision from to AMDGPU: Fix not setting kill flag on temp reg when spilling.

arsenm updated this object.

arsenm added a subscriber: llvm-commits.

LGTM.

This revision is now accepted and ready to land.Nov 23 2016, 12:35 PM

r287808

Path

Size

lib/

Target/

AMDGPU/

2 lines

Show First 20 Lines • Show All 471 Lines • ▼ Show 20 Lines	for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += EltSize) {
}		}

MachinePointerInfo PInfo = BasePtrInfo.getWithOffset(EltSize * i);		MachinePointerInfo PInfo = BasePtrInfo.getWithOffset(EltSize * i);
MachineMemOperand *NewMMO		MachineMemOperand *NewMMO
= MF->getMachineMemOperand(PInfo, MMO->getFlags(),		= MF->getMachineMemOperand(PInfo, MMO->getFlags(),
EltSize, MinAlign(Align, EltSize * i));		EltSize, MinAlign(Align, EltSize * i));

auto MIB = BuildMI(*MBB, MI, DL, Desc)		auto MIB = BuildMI(*MBB, MI, DL, Desc)
.addReg(SubReg, getDefRegState(!IsStore))		.addReg(SubReg, getDefRegState(!IsStore) \| getKillRegState(IsKill))
.addReg(ScratchRsrcReg)		.addReg(ScratchRsrcReg)
.addReg(SOffset, SOffsetRegState)		.addReg(SOffset, SOffsetRegState)
.addImm(Offset)		.addImm(Offset)
.addImm(0) // glc		.addImm(0) // glc
.addImm(0) // slc		.addImm(0) // slc
.addImm(0) // tfe		.addImm(0) // tfe
.addMemOperand(NewMMO);		.addMemOperand(NewMMO);

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