TableGen: Allow signed immediates for instruction aliases

[arsenm]

LGTM

llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp

for (auto &Alias : Aliases.second) {
           break;
         }
         case CodeGenInstAlias::ResultOperand::K_Imm: {
           // Just because the alias has an immediate result, doesn't mean the
           // MCInst will. An MCExpr could be present, for example.
           IAP.addCond(Op + ".isImm()");
 
           Cond = Op + ".getImm() == " +
-                 llvm::utostr(CGA.ResultOperands[i].getImm());
+                 llvm::itostr(CGA.ResultOperands[i].getImm());
           IAP.addCond(Cond);
           break;
         }
         case CodeGenInstAlias::ResultOperand::K_Reg:
           // If this is zero_reg, something's playing tricks we're not
           // equipped to handle.
           if (!CGA.ResultOperands[i].getRegister()) {
             CantHandle = true;