[X86][LMT] Restrict nop length to one

[AsafBadouh]

Summary

not all lakemont MCU support long nop.
we can't assume we can generate long nop by default for MCU.

[aaboud]

Look good to me

lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

84

Maybe it worth adding a comment here explaining why you are preventing generating long nops for lakemont.

test/MC/X86/x86_long_nop.s

19–20

You may fit the comment in one line now, it will be still less than 80 characters.

[zvi]

lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

80

Not related to this patch, but as a follow-up work, consider replacing this big condition with string compares with a new subtarget feature (in X86.td).

[zansari]

lgmt.. At some point, we'll need to add support for the different "lakemont" processors so that we don't affect them all with changes like this.

lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

 
 class X86AsmBackend : public MCAsmBackend {
   const StringRef CPU;
   bool HasNopl;
   const uint64_t MaxNopLength;
 public:
   X86AsmBackend(const Target &T, StringRef CPU)
       : MCAsmBackend(), CPU(CPU),
-        MaxNopLength((CPU == "slm" || CPU == "lakemont") ? 7 : 15) {
+        MaxNopLength((CPU == "slm") ? 7 : 15) {
     HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
               CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
               CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" &&
               CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" &&
-              CPU != "c3" && CPU != "c3-2";
+              CPU != "c3" && CPU != "c3-2" && CPU != "lakemont";
   }
 
   unsigned getNumFixupKinds() const override {
     return X86::NumTargetFixupKinds;
   }
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {

test/MC/X86/x86_long_nop.s

 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-apple-darwin10.0 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-apple-darwin8 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=slm %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=lakemont %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=lakemont %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=NOP1 %s
 
 # Ensure alignment directives also emit sequences of 15-byte NOPs on processors
 # capable of using long NOPs.
 inc %eax
 .p2align 5
 inc %eax
 # CHECK: 0:  inc
 # CHECK-NEXT: 1:  nop
 # CHECK-NEXT: 10:  nop
 # CHECK-NEXT: 1f:  nop
 # CHECK-NEXT: 20:  inc
 
-# On Silvermont and Lakemont we emit only 7 byte NOPs since longer NOPs
+# On Silvermont we emit only 7 byte NOPs since longer NOPs
 # are not profitable.
 # LNOP7: 0:  inc
 # LNOP7-NEXT: 1:  nop
 # LNOP7-NEXT: 8:  nop
 # LNOP7-NEXT: f:  nop
 # LNOP7-NEXT: 16:  nop
 # LNOP7-NEXT: 1d:  nop
 # LNOP7-NEXT: 20:  inc
+
+# On Lakemont we emit only 1 byte NOPs since longer NOPs are not supported/legal
+# NOP1: 0:  inc
+# NOP1-NEXT: 1:  nop
+# NOP1-NEXT: 2:  nop
+# NOP1-NEXT: 3:  nop
+# NOP1-NEXT: 4:  nop
+# NOP1-NEXT: 5:  nop
+# NOP1-NEXT: 6:  nop
+# .......
+# NOP1: 17:  nop
+# NOP1-NEXT: 18:  nop
+# NOP1-NEXT: 19:  nop
+# NOP1-NEXT: 1a:  nop
+# NOP1-NEXT: 1b:  nop
+# NOP1-NEXT: 1c:  nop
+# NOP1-NEXT: 1d:  nop
+# NOP1-NEXT: 1e:  nop
+# NOP1-NEXT: 1f:  nop
+# NOP1-NEXT: 20:  inc