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AMDGPU: Set hasExtraSrcRegAllocReq on v_div_scale_*
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Authored by arsenm on Nov 8 2016, 7:39 AM.

Reviewers

• tstellarAMD

Summary

This doesn't solve any problems I know about, but this should have more conservative assumptions about the operands

arsenm retitled this revision from to AMDGPU: Set hasExtraSrcRegAllocReq on v_div_scale_*.

arsenm updated this object.

arsenm added a subscriber: llvm-commits.

LGTM.

This revision is now accepted and ready to land.Nov 14 2016, 3:50 PM

r286913

Path

Size

lib/

Target/

AMDGPU/

2 lines

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	}			}

	defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",			defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",
	VOP_I32_I32_I32, mulhs			VOP_I32_I32_I32, mulhs
	>;			>;

	} // End isCommutable = 1, SchedRW = [WriteQuarterRate32]			} // End isCommutable = 1, SchedRW = [WriteQuarterRate32]

	let SchedRW = [WriteFloatFMA, WriteSALU] in {			let SchedRW = [WriteFloatFMA, WriteSALU], hasExtraSrcRegAllocReq = 1 in {
	defm V_DIV_SCALE_F32 : VOP3bInst <vop3<0x16d, 0x1e0>, "v_div_scale_f32",			defm V_DIV_SCALE_F32 : VOP3bInst <vop3<0x16d, 0x1e0>, "v_div_scale_f32",
	VOP3b_F32_I1_F32_F32_F32, [], 1			VOP3b_F32_I1_F32_F32_F32, [], 1
	>;			>;
	}			}

	let SchedRW = [WriteDouble, WriteSALU] in {			let SchedRW = [WriteDouble, WriteSALU] in {
	// Double precision division pre-scale.			// Double precision division pre-scale.
	defm V_DIV_SCALE_F64 : VOP3bInst <vop3<0x16e, 0x1e1>, "v_div_scale_f64",			defm V_DIV_SCALE_F64 : VOP3bInst <vop3<0x16e, 0x1e1>, "v_div_scale_f64",
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