AMDGPU: Cleanup some xfailed tests

[arsenm]

Summary

Some of these are already fixed or tested somewhere else.

[• tstellarAMD]

LGTM.

[arsenm]

r285840

test/CodeGen/AMDGPU/simplify-demanded-bits-build-pair.ll

-; XFAIL: *
-; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI %s
-
-; 64-bit select was originally lowered with a build_pair, and this
-; could be simplified to 1 cndmask instead of 2, but that broken when
-; it started being implemented with a v2i32 build_vector and
-; bitcasting.
-define void @trunc_select_i64(i32 addrspace(1)* %out, i64 %a, i64 %b, i32 %c) {
-  %cmp = icmp eq i32 %c, 0
-  %select = select i1 %cmp, i64 %a, i64 %b
-  %trunc = trunc i64 %select to i32
-  store i32 %trunc, i32 addrspace(1)* %out, align 4
-  ret void
-}
-
-; FIXME: Fix truncating store for local memory
-; SI-LABEL: {{^}}trunc_load_alloca_i64:
-; SI: v_movrels_b32
-; SI-NOT: v_movrels_b32
-; SI: s_endpgm
-define void @trunc_load_alloca_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) {
-  %idx = add i32 %a, %b
-  %alloca = alloca i64, i32 4
-  %gep0 = getelementptr i64, i64* %alloca, i64 0
-  %gep1 = getelementptr i64, i64* %alloca, i64 1
-  %gep2 = getelementptr i64, i64* %alloca, i64 2
-  %gep3 = getelementptr i64, i64* %alloca, i64 3
-  store i64 24, i64* %gep0, align 8
-  store i64 9334, i64* %gep1, align 8
-  store i64 3935, i64* %gep2, align 8
-  store i64 9342, i64* %gep3, align 8
-  %gep = getelementptr i64, i64* %alloca, i32 %idx
-  %load = load i64, i64* %gep, align 8
-  %mask = and i64 %load, 4294967296
-  %add = add i64 %mask, -1
-  store i64 %add, i64 addrspace(1)* %out, align 4
-  ret void
-}

test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll

-; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN %s
-; XFAIL: *
+; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs -mattr=-promote-alloca,-load-store-opt < %s | FileCheck -check-prefix=GCN %s
 
-@sPrivateStorage = external addrspace(3) global [256 x [8 x <4 x i64>]]
+@sPrivateStorage = internal addrspace(3) global [256 x [8 x <4 x i64>]] undef
 
 ; GCN-LABEL: {{^}}ds_reorder_vector_split:
 
 ; Write zeroinitializer
 ; GCN-DAG: ds_write_b64 [[PTR:v[0-9]+]], [[VAL:v\[[0-9]+:[0-9]+\]]] offset:24
 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:16
 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:8
 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]]{{$}}
 
 ; GCN: s_waitcnt vmcnt
 
 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
+; Appears to be dead store of vector component.
+; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
 
-; GCN: s_waitcnt lgkmcnt
 
-; GCN-DAG ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:8
+; GCN-DAG: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:8
 ; GCN-DAG: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:16
 ; GCN-DAG: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:24
 
-; Appears to be dead store of vector component.
-; GCN: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
+; GCN-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
+; GCN-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
+; GCN-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16
+; GCN-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24
 
-; GCN: buffer_store_dwordx2
-; GCN: buffer_store_dwordx2
-; GCN: buffer_store_dwordx2
-; GCN: buffer_store_dwordx2
 ; GCN: s_endpgm
 define void @ds_reorder_vector_split(<4 x i64> addrspace(1)* nocapture readonly %srcValues, i32 addrspace(1)* nocapture readonly %offsets, <4 x i64> addrspace(1)* nocapture %destBuffer, i32 %alignmentOffset) #0 {
 entry:
   %tmp = tail call i32 @llvm.r600.read.local.size.y()
   %tmp1 = tail call i32 @llvm.r600.read.local.size.z()
   %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.x()
   %tmp3 = tail call i32 @llvm.amdgcn.workitem.id.y()
   %tmp4 = tail call i32 @llvm.amdgcn.workitem.id.z()

test/CodeGen/AMDGPU/store-global.ll

entry:
   %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0
   %1 = insertelement <2 x float> %0, float %b, i32 1
   store <2 x float> %1, <2 x float> addrspace(1)* %out
   ret void
 }
 
 ; FUNC-LABEL: {{^}}store_v3i32:
 ; GCN-DAG: buffer_store_dwordx2
-; GCN-DAG: buffer_store_dword
+; GCN-DAG: buffer_store_dword v
 
 ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.[XYZW]}}, {{T[0-9]+\.[XYZW]}},
 ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.XY}}, {{T[0-9]+\.[XYZW]}},
 define void @store_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a) nounwind {
   store <3 x i32> %a, <3 x i32> addrspace(1)* %out, align 16
   ret void
 }
 
entry:
   store i32 1, i32 addrspace(1)* %arrayidx2, align 4
   %arrayidx4 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 2
   store i32 2, i32 addrspace(1)* %arrayidx4, align 4
   %arrayidx6 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 3
   store i32 2, i32 addrspace(1)* %arrayidx6, align 4
   ret void
 }
 
-
 attributes #0 = { nounwind }