ScheduleDAGInstrs: Ignore dependencies of constant physregs

[MatzeB]

Summary

There is no need to track dependencies for constant physregs, as they don't change their value no matter in what order you read/write to them.

[gberry]

This seems reasonable to me.

[MatzeB]

In D26221#589686, @gberry wrote:

This seems reasonable to me.

Reasonable enough for a "LGTM"?

[gberry]

Sure. I took a look at some of the assembly diffs and I'm curious to know if you observed any significant performance gains with the increased scheduling freedom?

[MatzeB]

In D26221#592333, @gberry wrote:

Sure. I took a look at some of the assembly diffs and I'm curious to know if you observed any significant performance gains with the increased scheduling freedom?

You probably will not see any change in codegen with this patch alone.

However when applying https://reviews.llvm.org/D26111 there are some regressions which get fixed by this patch. And with D26111 I see some smaller improvements in codesize and performance (because we effectively decrease register pressure when replacing with the zero register early).

llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

 
 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
 /// this SUnit to following instructions in the same scheduling region that
 /// depend the physical register referenced at OperIdx.
 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
   MachineInstr *MI = SU->getInstr();
   MachineOperand &MO = MI->getOperand(OperIdx);
   unsigned Reg = MO.getReg();
+  // We do not need to track any dependencies for constant registers.
+  if (MRI.isConstantPhysReg(Reg))
+    return;
 
   // Optionally add output and anti dependencies. For anti
   // dependencies we use a latency of 0 because for a multi-issue
   // target we want to allow the defining instruction to issue
   // in the same cycle as the using instruction.
   // TODO: Using a latency of 1 here for output dependencies assumes
   //       there's no cost for reusing registers.
   SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;

llvm/trunk/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll

 ; RUN: llc < %s -mtriple=aarch64-apple-ios -fast-isel -verify-machineinstrs | FileCheck %s
 
 ; Check that the kill flag is cleared between CSE'd instructions on their
 ; imp-def'd registers.
 ; The verifier would complain otherwise.
 define i64 @csed-impdef-killflag(i64 %a) {
 ; CHECK-LABEL: csed-impdef-killflag
 ; CHECK-DAG:  orr    [[REG1:w[0-9]+]], wzr, #0x1
 ; CHECK-DAG:  orr    [[REG2:x[0-9]+]], xzr, #0x2
 ; CHECK-DAG:  orr    [[REG3:x[0-9]+]], xzr, #0x3
-; CHECK:      cmp    x0, #0
-; CHECK-DAG:  csel   w[[SELECT_WREG_1:[0-9]+]], wzr, [[REG1]], ne
+; CHECK-DAG:  cmp    x0, #0
+; CHECK:  csel   w[[SELECT_WREG_1:[0-9]+]], wzr, [[REG1]], ne
 ; CHECK-DAG:  csel   [[SELECT_XREG_2:x[0-9]+]], [[REG2]], [[REG3]], ne
 ; CHECK:      ubfx   [[SELECT_XREG_1:x[0-9]+]], x[[SELECT_WREG_1]], #0, #32
 ; CHECK-NEXT: add    x0, [[SELECT_XREG_2]], [[SELECT_XREG_1]]
 ; CHECK-NEXT: ret
 
   %1 = icmp ne i64 %a, 0
   %2 = select i1 %1, i32 0, i32 1
   %3 = icmp ne i64 %a, 0
   %4 = select i1 %3, i64 2, i64 3
   %5 = zext i32 %2 to i64
   %6 = add i64 %4, %5
   ret i64 %6
 }

llvm/trunk/test/CodeGen/AArch64/scheduledag-constreg.mir

+# RUN: llc -o /dev/null %s -mtriple=aarch64-- -run-pass=machine-scheduler -enable-misched -debug-only=misched 2>&1 | FileCheck %s
+# REQUIRES: asserts
+--- |
+  define void @func() { ret void }
+...
+---
+# Check that the instructions are not dependent on each other, even though
+# they all read/write to the zero register.
+# CHECK-LABEL: MI Scheduling
+# CHECK: SU(0): %WZR<def,dead> = SUBSWri %W1, 0, 0, %NZCV<imp-def,dead>
+# CHECK: # succs left : 0
+# CHECK-NOT: Successors:
+# CHECK: SU(1): %W2<def> = COPY %WZR
+# CHECK: # succs left : 0
+# CHECK-NOT: Successors:
+# CHECK: SU(2): %WZR<def,dead> = SUBSWri %W3, 0, 0, %NZCV<imp-def,dead>
+# CHECK: # succs left : 0
+# CHECK-NOT: Successors:
+# CHECK: SU(3): %W4<def> = COPY %WZR
+# CHECK: # succs left : 0
+# CHECK-NOT: Successors:
+name: func
+body: |
+  bb.0:
+    dead %wzr = SUBSWri %w1, 0, 0, implicit-def dead %nzcv
+    %w2 = COPY %wzr
+    dead %wzr = SUBSWri %w3, 0, 0, implicit-def dead %nzcv
+    %w4 = COPY %wzr
+...

llvm/trunk/test/CodeGen/AArch64/subs-to-sub-opt.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu -O3 -o - %s | FileCheck %s
 
 @a = external global i8, align 1
 @b = external global i8, align 1
 
 ; Test that SUBS is replaced by SUB if condition flags are not used.
 define i32 @test01() nounwind {
 ; CHECK: ldrb {{.*}}
 ; CHECK-NEXT: ldrb {{.*}}
-; CHECK-NEXT: sub {{.*}}
+; CHECK: sub {{.*}}
 ; CHECK-NEXT: cmn {{.*}}
 entry:
   %0 = load i8, i8* @a, align 1
   %conv = zext i8 %0 to i32
   %1 = load i8, i8* @b, align 1
   %conv1 = zext i8 %1 to i32
   %s = sub nsw i32 %conv1, %conv
   %cmp0 = icmp eq i32 %s, -1
   %cmp1 = sext i1 %cmp0 to i8
   store i8 %cmp1, i8* @a
   ret i32 0
 }