[PowerPC] - No SExt/ZExt needed for count trailing zeros

[nemanjai]

Summary

Power9 provides the cnttzw instruction. However, in 64-bit mode, the instruction is followed by a clrldi instruction which is redundant. This patch provides the same handling for this issue as was done with cntlzw.

[kbarton]

LGTM

[nemanjai]

Committed revision 285267.

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

static bool PeepholePPC64ZExtGather(SDValue Op32,
 
   // LHBRX and LWBRX always clear the higher-order bits.
   if (Op32.getMachineOpcode() == PPC::LHBRX ||
       Op32.getMachineOpcode() == PPC::LWBRX) {
     ToPromote.insert(Op32.getNode());
     return true;
   }
 
-  // CNTLZW always produces a 64-bit value in [0,32], and so is zero extended.
-  if (Op32.getMachineOpcode() == PPC::CNTLZW) {
+  // CNT[LT]ZW always produce a 64-bit value in [0,32], and so is zero extended.
+  if (Op32.getMachineOpcode() == PPC::CNTLZW ||
+      Op32.getMachineOpcode() == PPC::CNTTZW) {
     ToPromote.insert(Op32.getNode());
     return true;
   }
 
   // Next, check for those instructions we can look through.
 
   // Assuming the mask does not wrap around, then the higher-order bits are
   // taken directly from the first operand.
for (SDNode *PN : ToPromote) {
       case PPC::RLWNM:     NewOpcode = PPC::RLWNM8; break;
       case PPC::SLW:       NewOpcode = PPC::SLW8; break;
       case PPC::SRW:       NewOpcode = PPC::SRW8; break;
       case PPC::LI:        NewOpcode = PPC::LI8; break;
       case PPC::LIS:       NewOpcode = PPC::LIS8; break;
       case PPC::LHBRX:     NewOpcode = PPC::LHBRX8; break;
       case PPC::LWBRX:     NewOpcode = PPC::LWBRX8; break;
       case PPC::CNTLZW:    NewOpcode = PPC::CNTLZW8; break;
+      case PPC::CNTTZW:    NewOpcode = PPC::CNTTZW8; break;
       case PPC::RLWIMI:    NewOpcode = PPC::RLWIMI8; break;
       case PPC::OR:        NewOpcode = PPC::OR8; break;
       case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
       case PPC::ORI:       NewOpcode = PPC::ORI8; break;
       case PPC::ORIS:      NewOpcode = PPC::ORIS8; break;
       case PPC::AND:       NewOpcode = PPC::AND8; break;
       case PPC::ANDIo:     NewOpcode = PPC::ANDIo8; break;
       case PPC::ANDISo:    NewOpcode = PPC::ANDISo8; break;

test/CodeGen/PowerPC/no-ext-with-count-zeros.ll

+; Function Attrs: nounwind readnone
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s
+
+define signext i32 @ctw(i32 signext %a) {
+entry:
+  %0 = tail call i32 @llvm.cttz.i32(i32 %a, i1 false)
+  ret i32 %0
+; CHECK-LABEL: ctw
+; CHECK: cnttzw 3, 3
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.cttz.i32(i32, i1)
+
+; Function Attrs: nounwind readnone
+define signext i32 @clw(i32 signext %a) {
+entry:
+  %0 = tail call i32 @llvm.ctlz.i32(i32 %a, i1 false)
+  ret i32 %0
+; CHECK-LABEL: clw
+; CHECK: cntlzw 3, 3
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ctlz.i32(i32, i1)
+
+; Function Attrs: nounwind readnone
+define i64 @ctd(i64 %a) {
+entry:
+  %0 = tail call i64 @llvm.cttz.i64(i64 %a, i1 false)
+  ret i64 %0
+; CHECK-LABEL: ctd
+; CHECK: cnttzd 3, 3
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.cttz.i64(i64, i1)
+
+; Function Attrs: nounwind readnone
+define i64 @cld(i64 %a) {
+entry:
+  %0 = tail call i64 @llvm.ctlz.i64(i64 %a, i1 false)
+  ret i64 %0
+; CHECK-LABEL: cld
+; CHECK: cntlzd 3, 3
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ctlz.i64(i64, i1)