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[AArch64] Corrected spill size for DDD register class. NFCI
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Authored by bjope on Oct 20 2016, 4:13 AM.

Details

Summary

The spill size was incorrectly set to 196 bits,
which isn't a multiple of 8. This problem was detected when
experimenting with asserts that the spill size should be a
multiple of the byte size.

New corrected value for the spill size is set to 192 bits.

Note that tablegen (RegisterInfoEmitter) will divide the
size set in the RegisterClass definition by 8. So this
change should not have any impact on the tablegen output
(trunc(192/8) == trunc(196/8) == 24 bytes).

Diff Detail

Repository
rL LLVM

Event Timeline

bjope updated this revision to Diff 75282.Oct 20 2016, 4:13 AM
bjope retitled this revision from to [AArch64] Corrected spill size for DDD register class. NFCI.
bjope updated this object.
t.p.northover accepted this revision.Oct 20 2016, 1:46 PM
t.p.northover edited edge metadata.

Looks fine to me. Thanks!

This revision is now accepted and ready to land.Oct 20 2016, 1:46 PM
This revision was automatically updated to reflect the committed changes.