[AArch64] Corrected spill size for DDD register class. NFCI

[bjope]

Summary

The spill size was incorrectly set to 196 bits,
which isn't a multiple of 8. This problem was detected when
experimenting with asserts that the spill size should be a
multiple of the byte size.

New corrected value for the spill size is set to 192 bits.

Note that tablegen (RegisterInfoEmitter) will divide the
size set in the RegisterClass definition by 8. So this
change should not have any impact on the tablegen output
(trunc(192/8) == trunc(196/8) == 24 bytes).

[t.p.northover]

Looks fine to me. Thanks!

llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td

def DSeqTriples : RegisterTuples<[dsub0, dsub1, dsub2],
                                   (rotl FPR64, 2)]>;
 def DSeqQuads : RegisterTuples<[dsub0, dsub1, dsub2, dsub3],
                                [(rotl FPR64, 0), (rotl FPR64, 1),
                                 (rotl FPR64, 2), (rotl FPR64, 3)]>;
 def DD   : RegisterClass<"AArch64", [untyped], 64, (add DSeqPairs)> {
   let Size = 128;
 }
 def DDD  : RegisterClass<"AArch64", [untyped], 64, (add DSeqTriples)> {
-  let Size = 196;
+  let Size = 192;
 }
 def DDDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqQuads)> {
   let Size = 256;
 }
 
 // Pairs, triples, and quads of 128-bit vector registers.
 def QSeqPairs : RegisterTuples<[qsub0, qsub1], [(rotl FPR128, 0), (rotl FPR128, 1)]>;
 def QSeqTriples : RegisterTuples<[qsub0, qsub1, qsub2],