Fix *_EXTEND_VECTOR_INREG legalization

[pirama]

Summary

While promoting *_EXTEND_VECTOR_INREG nodes whose inputs are already
promoted, perform the appropriate sign extension for the promoted node
before doing the *_EXTEND_VECTOR_INREG operation. If not, the undefined
high-order bits of the promoted operand may (a) be garbage inc ase of
zext) or (b) contribute the wrong sign-bit (in case of sext)

Updated the promote-vec3.ll test after this change. The diff shows
explicit zeroing in case of zext and intermediate sign extension in case
of sext.

[RKSimon]

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

3366 ↗

(On Diff #75205)

Either move the return into each case of the switch statement (to allow defaults to elegantly fall through) or provide an llvm_unreachable for default.

[pirama]

Added a default case to the switch statement.

[RKSimon]

LGTM

llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 
 SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
   EVT VT = N->getValueType(0);
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
   assert(NVT.isVector() && "This type must be promoted to a vector type");
 
   SDLoc dl(N);
 
-  // For operands whose TypeAction is to promote, the promoted node to construct
-  // a new *_EXTEND_VECTOR_INREG node.
+  // For operands whose TypeAction is to promote, extend the promoted node
+  // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
+  // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
+  // type..
   if (getTypeAction(N->getOperand(0).getValueType())
       == TargetLowering::TypePromoteInteger) {
-    SDValue Promoted = GetPromotedInteger(N->getOperand(0));
+    SDValue Promoted;
+
+    switch(N->getOpcode()) {
+      case ISD::SIGN_EXTEND_VECTOR_INREG:
+        Promoted = SExtPromotedInteger(N->getOperand(0));
+        break;
+      case ISD::ZERO_EXTEND_VECTOR_INREG:
+        Promoted = ZExtPromotedInteger(N->getOperand(0));
+        break;
+      case ISD::ANY_EXTEND_VECTOR_INREG:
+        Promoted = GetPromotedInteger(N->getOperand(0));
+        break;
+      default:
+        llvm_unreachable("Node has unexpected Opcode");
+    }
     return DAG.getNode(N->getOpcode(), dl, NVT, Promoted);
   }
 
   // Directly extend to the appropriate transform-to type.
   return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {

llvm/trunk/test/CodeGen/X86/promote-vec3.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=SSE3
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX-32
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX-32
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX-64
 
 define <3 x i16> @zext_i8(<3 x i8>) {
 ; SSE3-LABEL: zext_i8:
 ; SSE3:       # BB#0:
 ; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; SSE3-NEXT:    pinsrw $0, %eax, %xmm0
+; SSE3-NEXT:    pxor %xmm0, %xmm0
+; SSE3-NEXT:    pxor %xmm1, %xmm1
+; SSE3-NEXT:    pinsrw $0, %eax, %xmm1
 ; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; SSE3-NEXT:    pinsrw $1, %eax, %xmm0
+; SSE3-NEXT:    pinsrw $1, %eax, %xmm1
 ; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; SSE3-NEXT:    pinsrw $2, %eax, %xmm0
-; SSE3-NEXT:    pxor %xmm1, %xmm1
-; SSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSE3-NEXT:    movd %xmm0, %eax
-; SSE3-NEXT:    pextrw $2, %xmm0, %edx
-; SSE3-NEXT:    pextrw $4, %xmm0, %ecx
+; SSE3-NEXT:    pinsrw $2, %eax, %xmm1
+; SSE3-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; SSE3-NEXT:    movd %xmm1, %eax
+; SSE3-NEXT:    pextrw $2, %xmm1, %edx
+; SSE3-NEXT:    pextrw $4, %xmm1, %ecx
 ; SSE3-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; SSE3-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
 ; SSE3-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
 ; SSE3-NEXT:    retl
 ;
 ; SSE41-LABEL: zext_i8:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    pxor %xmm0, %xmm0

 ; SSE3-LABEL: sext_i8:
 ; SSE3:       # BB#0:
 ; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; SSE3-NEXT:    pinsrw $0, %eax, %xmm0
 ; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; SSE3-NEXT:    pinsrw $1, %eax, %xmm0
 ; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
 ; SSE3-NEXT:    pinsrw $2, %eax, %xmm0
+; SSE3-NEXT:    psllw $8, %xmm0
+; SSE3-NEXT:    psraw $8, %xmm0
 ; SSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
 ; SSE3-NEXT:    psrad $16, %xmm0
 ; SSE3-NEXT:    movd %xmm0, %eax
 ; SSE3-NEXT:    pextrw $2, %xmm0, %edx
 ; SSE3-NEXT:    pextrw $4, %xmm0, %ecx
 ; SSE3-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; SSE3-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
 ; SSE3-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>