[AMDGPU] Mark .note section SHF_ALLOC so lld creates a segment for it

[• tstellarAMD]

LGTM.

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() {
   return static_cast<MCELFStreamer &>(Streamer);
 }
 
 void
 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion(uint32_t Major,
                                                            uint32_t Minor) {
   MCStreamer &OS = getStreamer();
-  MCSectionELF *Note = OS.getContext().getELFSection(".note", ELF::SHT_NOTE, 0);
+  MCSectionELF *Note =
+      OS.getContext().getELFSection(".note", ELF::SHT_NOTE, ELF::SHF_ALLOC);
 
   unsigned NameSZ = 4;
 
   OS.PushSection();
   OS.SwitchSection(Note);
   OS.EmitIntValue(NameSZ, 4);                            // namesz
   OS.EmitIntValue(8, 4);                                 // descz
   OS.EmitIntValue(NT_AMDGPU_HSA_CODE_OBJECT_VERSION, 4); // type
   OS.EmitBytes(StringRef("AMD", NameSZ));                // name
   OS.EmitIntValue(Major, 4);                             // desc
   OS.EmitIntValue(Minor, 4);
   OS.EmitValueToAlignment(4);
   OS.PopSection();
 }
 
 void
 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major,
                                                        uint32_t Minor,
                                                        uint32_t Stepping,
                                                        StringRef VendorName,
                                                        StringRef ArchName) {
   MCStreamer &OS = getStreamer();
-  MCSectionELF *Note = OS.getContext().getELFSection(".note", ELF::SHT_NOTE, 0);
+  MCSectionELF *Note =
+      OS.getContext().getELFSection(".note", ELF::SHT_NOTE, ELF::SHF_ALLOC);
 
   unsigned NameSZ = 4;
   uint16_t VendorNameSize = VendorName.size() + 1;
   uint16_t ArchNameSize = ArchName.size() + 1;
   unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
                     sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
                     VendorNameSize + ArchNameSize;
 

llvm/trunk/test/CodeGen/AMDGPU/hsa.ll

 ; ELF: Name: .text
 ; ELF: Type: SHT_PROGBITS (0x1)
 ; ELF: Flags [ (0x6)
 ; ELF: SHF_ALLOC (0x2)
 ; ELF: SHF_EXECINSTR (0x4)
 ; ELF: }
 
 ; ELF: SHT_NOTE
+; ELF: Flags [ (0x2)
+; ELF: SHF_ALLOC (0x2)
+; ELF: ]
+; ELF: SectionData (
 ; ELF: 0000: 04000000 08000000 01000000 414D4400
 ; ELF: 0010: 02000000 01000000 04000000 1B000000
 ; ELF: 0020: 03000000 414D4400 04000700 07000000
 ; ELF: 0030: 00000000 00000000 414D4400 414D4447
 ; ELF: 0040: 50550000
+; ELF: )
 
 ; ELF: Symbol {
 ; ELF: Name: simple
 ; ELF: Size: 288
 ; ELF: Type: AMDGPU_HSA_KERNEL (0xA)
 ; ELF: }
 
 ; HSA: .hsa_code_object_version 2,1