[PPC] Shorter sequence to load 64bit constant with same hi/lo words

[Carrot]

Summary

This is a patch to implement pr30640.

When a 64bit constant has the same hi/lo words, we can use rldimi to copy the low word into high word of the same register.

This optimization caused failure of test case bperm.ll because of not optimal heuristic in function SelectAndParts64. It chooses AND or ROTATE to extract bit groups from a register, and OR them together. This optimization lowers the cost of loading 64bit constant mask used in AND method, and causes different code sequence. But actually ROTATE method is better in this test case. The reason is in ROTATE method the final OR operation can be avoided since rldimi can insert the rotated bits into target register directly. So this patch also enhances SelectAndParts64 to prefer ROTATE method when the two methods have same cost and there are multiple bit groups need to be ORed together.

[hfinkel]

LGTM

test/CodeGen/PowerPC/pr30640.ll

7

Please check the full materialization sequence.

[Carrot]

Updated the test case with full related code sequence.

[hfinkel]

test/CodeGen/PowerPC/pr30640.ll

9

Please use regexs here to avoid a dependence on unrelated RA choices:

; CHECK: lis [[REG1:[0-9]+]], -12851
; CHECK: ori [[REG2:[0-9]+]], [[REG1]], 52685

and so on. Only the output register is fixed.

[Carrot]

Updated test case with regex.

[hfinkel]

In D25521#569623, @Carrot wrote:

Updated test case with regex.

LGTM

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

static unsigned getInt64CountDirect(int64_t Imm) {
   } else {
     // Just the Hi bits.
     ++Result;
   }
 
   // If no shift, we're done.
   if (!Shift) return Result;
 
+  // If Hi word == Lo word,
+  // we can use rldimi to insert the Lo word into Hi word.
+  if ((unsigned)(Imm & 0xFFFFFFFF) == Remainder) {
+    ++Result;
+    return Result;
+  }
+
   // Shift for next step if the upper 32-bits were not zero.
   if (Imm)
     ++Result;
 
   // Add in the last bits as required.
   if ((Remainder >> 16) & 0xFFFF)
     ++Result;
   if (Remainder & 0xFFFF)
static SDNode *getInt64Direct(SelectionDAG *CurDAG, const SDLoc &dl,
   } else {
     // Just the Hi bits.
     Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
   }
 
   // If no shift, we're done.
   if (!Shift) return Result;
 
+  // If Hi word == Lo word,
+  // we can use rldimi to insert the Lo word into Hi word.
+  if ((unsigned)(Imm & 0xFFFFFFFF) == Remainder) {
+    SDValue Ops[] =
+      { SDValue(Result, 0), SDValue(Result, 0), getI32Imm(Shift), getI32Imm(0)};
+    return CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops);
+  }
+
   // Shift for next step if the upper 32-bits were not zero.
   if (Imm) {
     Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
                                     SDValue(Result, 0),
                                     getI32Imm(Shift),
                                     getI32Imm(63 - Shift));
   }
 
for (ValueRotInfo &VRI : ValueRotsVec) {
       if (Use32BitInsts)
         NumAndInsts += (unsigned) (ANDIMask != 0) + (unsigned) (ANDISMask != 0) +
                        (unsigned) (ANDIMask != 0 && ANDISMask != 0);
       else
         NumAndInsts += getInt64Count(Mask) + /* and */ 1;
 
       unsigned NumRLInsts = 0;
       bool FirstBG = true;
+      bool MoreBG = false;
       for (auto &BG : BitGroups) {
-        if (!MatchingBG(BG))
+        if (!MatchingBG(BG)) {
+          MoreBG = true;
           continue;
+        }
         NumRLInsts +=
           SelectRotMask64Count(BG.RLAmt, BG.Repl32, BG.StartIdx, BG.EndIdx,
                                !FirstBG);
         FirstBG = false;
       }
 
       DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
                       " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":") <<
                       "\n\t\t\tisel using masking: " << NumAndInsts <<
                       " using rotates: " << NumRLInsts << "\n");
 
       // When we'd use andi/andis, we bias toward using the rotates (andi only
       // has a record form, and is cracked on POWER cores). However, when using
       // general 64-bit constant formation, bias toward the constant form,
       // because that exposes more opportunities for CSE.
       if (NumAndInsts > NumRLInsts)
         continue;
-      if (Use32BitInsts && NumAndInsts == NumRLInsts)
+      // When merging multiple bit groups, instruction or is used.
+      // But when rotate is used, rldimi can inert the rotated value into any
+      // register, so instruction or can be avoided.
+      if ((Use32BitInsts || MoreBG) && NumAndInsts == NumRLInsts)
         continue;
 
       DEBUG(dbgs() << "\t\t\t\tusing masking\n");
 
       if (InstCnt) *InstCnt += NumAndInsts;
 
       SDValue VRot;
       // We actually need to generate a rotation if we have a non-zero rotation

test/CodeGen/PowerPC/pr30640.ll

+; RUN: llc -O2  -march=ppc64 -mcpu=pwr8 < %s | FileCheck %s
+
+define i64 @foo() {
+entry:
+  ret i64 -3617008641903833651
+
+; CHECK: rldimi
+}
+