Handle *_EXTEND_VECTOR_INREG during Integer Legalization

[pirama]

Summary

These nodes need legalization for 3-element vectors. This commit
handles the legalization and adds tests for zext and sext.

This fixes PR30614.

[RKSimon]

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

3355

Are you sure we're correctly handling the extension in this case? Promotion tends to leave the upper bits as garbage - won't we still need to perform a SIGN_EXTEND_INREG/ZERO_EXTEND_INREG.

test/CodeGen/X86/promote-vec3.ll

2

Please use an -mattr=+ssse3 instead of a specific cpu target. Also test for SSE4.1 / AVX / AVX2 cases as well if you can, even though these probably don't use this new code path - just to check codegen.

Also please regenerate with utils\update_llc_test_checks.py

[pirama]

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

3355

Aah, that's right. I couldn't craft a test IR where an EXTEND_VECTOR_INREG gets generated by DAGCombine that matches the actual TransformTo type. Maybe this is infeasible. I'll remove this separate handling.

test/CodeGen/X86/promote-vec3.ll

2

'll add your suggested changes to this test.

I ran update_llc_test_checks and the checks seem to hard-code registers. Is this fine? (I've had issues in the past where hard-coded register values cause test failures on some bots where the RA picked a different set of registers).

[pirama]

Removed direct reuse of promoted operand because it may not be extended properly.

Update test commands and generate checks using update_llc_test_checks.py.

[RKSimon]

That's some pretty ugly codegen, but at least it doesn't crash any more!

One minor request but otherwise LGTM.

test/CodeGen/X86/promote-vec3.ll

2

You've set the triple so this should be fine. Although its more likely that future changes may alter the (awful) codegen, the fact that its generated from the script makes it trivial to update.

5

Please can you add at least one x86_64 test case?

[pirama]

Added x86_64 test for AVX2.

[pirama]

Thanks for the review Simon. I've added the x86_64 test and committed this in r283496.

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

case ISD::INSERT_VECTOR_ELT:
                          Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
   case ISD::BUILD_VECTOR:
                          Res = PromoteIntRes_BUILD_VECTOR(N); break;
   case ISD::SCALAR_TO_VECTOR:
                          Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
   case ISD::CONCAT_VECTORS:
                          Res = PromoteIntRes_CONCAT_VECTORS(N); break;
 
+  case ISD::ANY_EXTEND_VECTOR_INREG:
+  case ISD::SIGN_EXTEND_VECTOR_INREG:
+  case ISD::ZERO_EXTEND_VECTOR_INREG:
+                         Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
+
   case ISD::SIGN_EXTEND:
   case ISD::ZERO_EXTEND:
   case ISD::ANY_EXTEND:  Res = PromoteIntRes_INT_EXTEND(N); break;
 
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:  Res = PromoteIntRes_FP_TO_XINT(N); break;
 
   case ISD::FP_TO_FP16:  Res = PromoteIntRes_FP_TO_FP16(N); break;
for (unsigned j = 0; j < NumElem; ++j) {
           DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
       Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
     }
   }
 
   return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
 }
 
+SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
+  EVT VT = N->getValueType(0);
+  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
+  assert(NVT.isVector() && "This type must be promoted to a vector type");
+
+  SDLoc dl(N);
+
+  // For operands whose TypeAction is to promote, the promoted node to construct
+  // a new *_EXTEND_VECTOR_INREG node.
+  if (getTypeAction(N->getOperand(0).getValueType())
+      == TargetLowering::TypePromoteInteger) {
+    SDValue Promoted = GetPromotedInteger(N->getOperand(0));
+    return DAG.getNode(N->getOpcode(), dl, NVT, Promoted);
+  }
+
+  // Directly extend to the appropriate transform-to type.
+  return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
+}
+
 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
   EVT OutVT = N->getValueType(0);
   EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
   assert(NOutVT.isVector() && "This type must be promoted to a vector type");
 
   EVT NOutVTElem = NOutVT.getVectorElementType();
 
   SDLoc dl(N);

lib/CodeGen/SelectionDAG/LegalizeTypes.h

private:
   SDValue PromoteIntRes_AssertZext(SDNode *N);
   SDValue PromoteIntRes_Atomic0(AtomicSDNode *N);
   SDValue PromoteIntRes_Atomic1(AtomicSDNode *N);
   SDValue PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N, unsigned ResNo);
   SDValue PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N);
   SDValue PromoteIntRes_VECTOR_SHUFFLE(SDNode *N);
   SDValue PromoteIntRes_BUILD_VECTOR(SDNode *N);
   SDValue PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N);
+  SDValue PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N);
   SDValue PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N);
   SDValue PromoteIntRes_CONCAT_VECTORS(SDNode *N);
   SDValue PromoteIntRes_BITCAST(SDNode *N);
   SDValue PromoteIntRes_BSWAP(SDNode *N);
   SDValue PromoteIntRes_BITREVERSE(SDNode *N);
   SDValue PromoteIntRes_BUILD_PAIR(SDNode *N);
   SDValue PromoteIntRes_Constant(SDNode *N);
   SDValue PromoteIntRes_CONVERT_RNDSAT(SDNode *N);

test/CodeGen/X86/promote-vec3.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=SSE3
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX_ANY
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX_ANY
+
+define <3 x i16> @zext_i8(<3 x i8>) {
+; SSE3-LABEL: zext_i8:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; SSE3-NEXT:    pinsrw $0, %eax, %xmm0
+; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; SSE3-NEXT:    pinsrw $1, %eax, %xmm0
+; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; SSE3-NEXT:    pinsrw $2, %eax, %xmm0
+; SSE3-NEXT:    pxor %xmm1, %xmm1
+; SSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; SSE3-NEXT:    movd %xmm0, %eax
+; SSE3-NEXT:    pextrw $2, %xmm0, %edx
+; SSE3-NEXT:    pextrw $4, %xmm0, %ecx
+; SSE3-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE3-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
+; SSE3-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
+; SSE3-NEXT:    retl
+;
+; SSE41-LABEL: zext_i8:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pxor %xmm0, %xmm0
+; SSE41-NEXT:    pinsrb $0, {{[0-9]+}}(%esp), %xmm0
+; SSE41-NEXT:    pinsrb $4, {{[0-9]+}}(%esp), %xmm0
+; SSE41-NEXT:    pinsrb $8, {{[0-9]+}}(%esp), %xmm0
+; SSE41-NEXT:    movd %xmm0, %eax
+; SSE41-NEXT:    pextrw $2, %xmm0, %edx
+; SSE41-NEXT:    pextrw $4, %xmm0, %ecx
+; SSE41-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE41-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
+; SSE41-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
+; SSE41-NEXT:    retl
+;
+; AVX_ANY-LABEL: zext_i8:
+; AVX_ANY:       # BB#0:
+; AVX_ANY-NEXT:    vpxor %xmm0, %xmm0, %xmm0
+; AVX_ANY-NEXT:    vpinsrb $0, {{[0-9]+}}(%esp), %xmm0, %xmm0
+; AVX_ANY-NEXT:    vpinsrb $4, {{[0-9]+}}(%esp), %xmm0, %xmm0
+; AVX_ANY-NEXT:    vpinsrb $8, {{[0-9]+}}(%esp), %xmm0, %xmm0
+; AVX_ANY-NEXT:    vmovd %xmm0, %eax
+; AVX_ANY-NEXT:    vpextrw $2, %xmm0, %edx
+; AVX_ANY-NEXT:    vpextrw $4, %xmm0, %ecx
+; AVX_ANY-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX_ANY-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
+; AVX_ANY-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
+; AVX_ANY-NEXT:    retl
+  %2 = zext <3 x i8> %0 to <3 x i16>
+  ret <3 x i16> %2
+}
+
+define <3 x i16> @sext_i8(<3 x i8>) {
+; SSE3-LABEL: sext_i8:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; SSE3-NEXT:    pinsrw $0, %eax, %xmm0
+; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; SSE3-NEXT:    pinsrw $1, %eax, %xmm0
+; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; SSE3-NEXT:    pinsrw $2, %eax, %xmm0
+; SSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
+; SSE3-NEXT:    psrad $16, %xmm0
+; SSE3-NEXT:    movd %xmm0, %eax
+; SSE3-NEXT:    pextrw $2, %xmm0, %edx
+; SSE3-NEXT:    pextrw $4, %xmm0, %ecx
+; SSE3-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE3-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
+; SSE3-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
+; SSE3-NEXT:    retl
+;
+; SSE41-LABEL: sext_i8:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pinsrb $0, {{[0-9]+}}(%esp), %xmm0
+; SSE41-NEXT:    pinsrb $4, {{[0-9]+}}(%esp), %xmm0
+; SSE41-NEXT:    pinsrb $8, {{[0-9]+}}(%esp), %xmm0
+; SSE41-NEXT:    pslld $24, %xmm0
+; SSE41-NEXT:    psrad $24, %xmm0
+; SSE41-NEXT:    movd %xmm0, %eax
+; SSE41-NEXT:    pextrw $2, %xmm0, %edx
+; SSE41-NEXT:    pextrw $4, %xmm0, %ecx
+; SSE41-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE41-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
+; SSE41-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
+; SSE41-NEXT:    retl
+;
+; AVX_ANY-LABEL: sext_i8:
+; AVX_ANY:       # BB#0:
+; AVX_ANY-NEXT:    vpinsrb $0, {{[0-9]+}}(%esp), %xmm0, %xmm0
+; AVX_ANY-NEXT:    vpinsrb $4, {{[0-9]+}}(%esp), %xmm0, %xmm0
+; AVX_ANY-NEXT:    vpinsrb $8, {{[0-9]+}}(%esp), %xmm0, %xmm0
+; AVX_ANY-NEXT:    vpslld $24, %xmm0, %xmm0
+; AVX_ANY-NEXT:    vpsrad $24, %xmm0, %xmm0
+; AVX_ANY-NEXT:    vmovd %xmm0, %eax
+; AVX_ANY-NEXT:    vpextrw $2, %xmm0, %edx
+; AVX_ANY-NEXT:    vpextrw $4, %xmm0, %ecx
+; AVX_ANY-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX_ANY-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
+; AVX_ANY-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
+; AVX_ANY-NEXT:    retl
+  %2 = sext <3 x i8> %0 to <3 x i16>
+  ret <3 x i16> %2
+}