AMDGPU: Use 1/2pi inline imm on VI

[arsenm]

Summary

I'm guessing at how it is supposed to be printed

[• tstellarAMD]

LGTM.

[arsenm]

r285490

lib/Target/AMDGPU/AMDGPU.td

 >;
 
 def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
   "HasSMemRealTime",
   "true",
   "Has s_memrealtime instruction"
 >;
 
+def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
+  "HasInv2PiInlineImm",
+  "true",
+  "Has 1 / (2 * pi) as inline immediate"
+>;
+
 def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
   "Has16BitInsts",
   "true",
   "Has i16/f16 instructions"
 >;
 
 //===------------------------------------------------------------===//
 // Subtarget Features (options and debugging)
def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
   FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
   FeatureGCN1Encoding, FeatureCIInsts]
 >;
 
 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
   [FeatureFP64, FeatureLocalMemorySize65536,
    FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
    FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
-   FeatureSMemRealTime
+   FeatureInv2PiInlineImm, FeatureSMemRealTime
   ]
 >;
 
 //===----------------------------------------------------------------------===//
 // Debugger related subtarget features.
 //===----------------------------------------------------------------------===//
 
 def FeatureDebuggerInsertNops : SubtargetFeature<

lib/Target/AMDGPU/AMDGPUSubtarget.h

protected:
   bool FP64;
   bool IsGCN;
   bool GCN1Encoding;
   bool GCN3Encoding;
   bool CIInsts;
   bool SGPRInitBug;
   bool HasSMemRealTime;
   bool Has16BitInsts;
+  bool HasInv2PiInlineImm;
   bool FlatAddressSpace;
   bool R600ALUInst;
   bool CaymanISA;
   bool CFALUBug;
   bool HasVertexCache;
   short TexVTXClauseSize;
 
   // Dummy feature to use for assembler in tablegen.
public:
   bool has16BitInsts() const {
     return Has16BitInsts;
   }
 
   bool hasScalarCompareEq64() const {
     return getGeneration() >= VOLCANIC_ISLANDS;
   }
 
+  bool hasInv2PiInlineImm() const {
+    return HasInv2PiInlineImm;
+  }
+
   bool enableSIScheduler() const {
     return EnableSIScheduler;
   }
 
   bool debuggerSupported() const {
     return debuggerInsertNops() && debuggerReserveRegs() &&
       debuggerEmitPrologue();
   }

lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h

void printDA(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                raw_ostream &O);
   void printR128(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                  raw_ostream &O);
   void printLWE(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                 raw_ostream &O);
   void printRegOperand(unsigned RegNo, raw_ostream &O);
   void printVOPDst(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                    raw_ostream &O);
-  void printImmediate32(uint32_t Imm, raw_ostream &O);
-  void printImmediate64(uint64_t Imm, raw_ostream &O);
+  void printImmediate32(uint32_t Imm, const MCSubtargetInfo &STI,
+                        raw_ostream &O);
+  void printImmediate64(uint64_t Imm, const MCSubtargetInfo &STI,
+                        raw_ostream &O);
   void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O);
   void printOperandAndFPInputMods(const MCInst *MI, unsigned OpNo,
                                   const MCSubtargetInfo &STI, raw_ostream &O);
   void printOperandAndIntInputMods(const MCInst *MI, unsigned OpNo,
                                    const MCSubtargetInfo &STI, raw_ostream &O);
   void printDPPCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O);

lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
   else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
     O << "_sdwa ";
   else
     O << "_e32 ";
 
   printOperand(MI, OpNo, STI, O);
 }
 
-void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) {
+void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
+                                         const MCSubtargetInfo &STI,
+                                         raw_ostream &O) {
   int32_t SImm = static_cast<int32_t>(Imm);
   if (SImm >= -16 && SImm <= 64) {
     O << SImm;
     return;
   }
 
   if (Imm == FloatToBits(0.0f))
     O << "0.0";
   else if (Imm == FloatToBits(1.0f))
     O << "1.0";
   else if (Imm == FloatToBits(-1.0f))
     O << "-1.0";
   else if (Imm == FloatToBits(0.5f))
     O << "0.5";
   else if (Imm == FloatToBits(-0.5f))
     O << "-0.5";
   else if (Imm == FloatToBits(2.0f))
     O << "2.0";
   else if (Imm == FloatToBits(-2.0f))
     O << "-2.0";
   else if (Imm == FloatToBits(4.0f))
     O << "4.0";
   else if (Imm == FloatToBits(-4.0f))
     O << "-4.0";
+  else if (Imm == 0x3e22f983 &&
+           STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
+    O << "1/2pi";
   else
     O << formatHex(static_cast<uint64_t>(Imm));
 }
 
-void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, raw_ostream &O) {
+void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
+                                         const MCSubtargetInfo &STI,
+                                         raw_ostream &O) {
   int64_t SImm = static_cast<int64_t>(Imm);
   if (SImm >= -16 && SImm <= 64) {
     O << SImm;
     return;
   }
 
   if (Imm == DoubleToBits(0.0))
     O << "0.0";
   else if (Imm == DoubleToBits(1.0))
     O << "1.0";
   else if (Imm == DoubleToBits(-1.0))
     O << "-1.0";
   else if (Imm == DoubleToBits(0.5))
     O << "0.5";
   else if (Imm == DoubleToBits(-0.5))
     O << "-0.5";
   else if (Imm == DoubleToBits(2.0))
     O << "2.0";
   else if (Imm == DoubleToBits(-2.0))
     O << "-2.0";
   else if (Imm == DoubleToBits(4.0))
     O << "4.0";
   else if (Imm == DoubleToBits(-4.0))
     O << "-4.0";
+  else if (Imm == 0x3fc45f306dc9c882 &&
+           STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
+    O << "1/2pi";
   else {
     assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
 
     // In rare situations, we will have a 32-bit literal in a 64-bit
     // operand. This is technically allowed for the encoding of s_mov_b64.
     O << formatHex(static_cast<uint64_t>(Imm));
   }
 }
default:
       break;
     }
   } else if (Op.isImm()) {
     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
     int RCID = Desc.OpInfo[OpNo].RegClass;
     if (RCID != -1) {
       const MCRegisterClass &ImmRC = MRI.getRegClass(RCID);
       if (ImmRC.getSize() == 4)
-        printImmediate32(Op.getImm(), O);
+        printImmediate32(Op.getImm(), STI, O);
       else if (ImmRC.getSize() == 8)
-        printImmediate64(Op.getImm(), O);
+        printImmediate64(Op.getImm(), STI, O);
       else
         llvm_unreachable("Invalid register class size");
     } else if (Desc.OpInfo[OpNo].OperandType == MCOI::OPERAND_IMMEDIATE) {
-      printImmediate32(Op.getImm(), O);
+      printImmediate32(Op.getImm(), STI, O);
     } else {
       // We hit this for the immediate instruction bits that don't yet have a
       // custom printer.
       // TODO: Eventually this should be unnecessary.
       O << formatDec(Op.getImm());
     }
   } else if (Op.isFPImm()) {
     // We special case 0.0 because otherwise it will be printed as an integer.
     if (Op.getFPImm() == 0.0)
       O << "0.0";
     else {
       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
       const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
 
       if (ImmRC.getSize() == 4)
-        printImmediate32(FloatToBits(Op.getFPImm()), O);
+        printImmediate32(FloatToBits(Op.getFPImm()), STI, O);
       else if (ImmRC.getSize() == 8)
-        printImmediate64(DoubleToBits(Op.getFPImm()), O);
+        printImmediate64(DoubleToBits(Op.getFPImm()), STI, O);
       else
         llvm_unreachable("Invalid register class size");
     }
   } else if (Op.isExpr()) {
     const MCExpr *Exp = Op.getExpr();
     Exp->print(O, &MAI);
   } else {
     O << "/*INV_OP*/";

lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

if (Val == FloatToBits(-2.0f))
     return 245;
 
   if (Val == FloatToBits(4.0f))
     return 246;
 
   if (Val == FloatToBits(-4.0f))
     return 247;
 
-  if (AMDGPU::isVI(STI) && Val == 0x3e22f983) // 1/(2*pi)
+  if (Val == 0x3e22f983 && // 1.0 / (2.0 * pi)
+      STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
     return 248;
 
   return 255;
 }
 
 static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
   uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
   if (IntImm != 0)
if (Val == DoubleToBits(-2.0))
     return 245;
 
   if (Val == DoubleToBits(4.0))
     return 246;
 
   if (Val == DoubleToBits(-4.0))
     return 247;
 
-  if (AMDGPU::isVI(STI) && Val == 0x3fc45f306dc9c882) // 1/(2*pi)
+  if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi)
+      STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
     return 248;
 
   return 255;
 }
 
 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
                                          unsigned OpSize,
                                          const MCSubtargetInfo &STI) const {

lib/Target/AMDGPU/SIInstrInfo.cpp

if (Imm.getBitWidth() == 64) {
     return (DoubleToBits(0.0) == Val) ||
            (DoubleToBits(1.0) == Val) ||
            (DoubleToBits(-1.0) == Val) ||
            (DoubleToBits(0.5) == Val) ||
            (DoubleToBits(-0.5) == Val) ||
            (DoubleToBits(2.0) == Val) ||
            (DoubleToBits(-2.0) == Val) ||
            (DoubleToBits(4.0) == Val) ||
-           (DoubleToBits(-4.0) == Val);
+           (DoubleToBits(-4.0) == Val) ||
+           (ST.hasInv2PiInlineImm() && Val == 0x3fc45f306dc9c882);
   }
 
   // The actual type of the operand does not seem to matter as long
   // as the bits match one of the inline immediate values.  For example:
   //
   // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
   // so it is a legal inline immediate.
   //
   // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
   // floating-point, so it is a legal inline immediate.
   uint32_t Val = Imm.getZExtValue();
 
   return (FloatToBits(0.0f) == Val) ||
          (FloatToBits(1.0f) == Val) ||
          (FloatToBits(-1.0f) == Val) ||
          (FloatToBits(0.5f) == Val) ||
          (FloatToBits(-0.5f) == Val) ||
          (FloatToBits(2.0f) == Val) ||
          (FloatToBits(-2.0f) == Val) ||
          (FloatToBits(4.0f) == Val) ||
-         (FloatToBits(-4.0f) == Val);
+         (FloatToBits(-4.0f) == Val) ||
+         (ST.hasInv2PiInlineImm() && Val == 0x3e22f983);
 }
 
 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
                                    unsigned OpSize) const {
   if (MO.isImm()) {
     // MachineOperand provides no way to tell the true operand size, since it
     // only records a 64-bit value. We need to know the size to determine if a
     // 32-bit floating point immediate bit pattern is legal for an integer

test/CodeGen/AMDGPU/imm.ll

 ; GCN-LABEL: {{^}}store_inline_imm_m_4.0_f32:
 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], -4.0{{$}}
 ; GCN: buffer_store_dword [[REG]]
 define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) {
   store float -4.0, float addrspace(1)* %out
   ret void
 }
 
+
+; GCN-LABEL: {{^}}store_inline_imm_inv_2pi_f32:
+; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e22f983{{$}}
+; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 1/2pi{{$}}
+; GCN: buffer_store_dword [[REG]]
+define void @store_inline_imm_inv_2pi_f32(float addrspace(1)* %out) {
+  store float 0x3FC45F3060000000, float addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}store_inline_imm_m_inv_2pi_f32:
+; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xbe22f983{{$}}
+; GCN: buffer_store_dword [[REG]]
+define void @store_inline_imm_m_inv_2pi_f32(float addrspace(1)* %out) {
+  store float 0xBFC45F3060000000, float addrspace(1)* %out
+  ret void
+}
+
 ; GCN-LABEL: {{^}}store_literal_imm_f32:
 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x45800000
 ; GCN: buffer_store_dword [[REG]]
 define void @store_literal_imm_f32(float addrspace(1)* %out) {
   store float 4096.0, float addrspace(1)* %out
   ret void
 }
 

 ; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -4.0
 ; GCN: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, -4.0
   store double %y, double addrspace(1)* %out
   ret void
 }
 
+; GCN-LABEL: {{^}}add_inline_imm_inv_2pi_f64:
+; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
+; SI-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0x6dc9c882
+; SI-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3fc45f30
+; SI: v_add_f64 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+
+; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
+; VI: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 1/2pi
+; VI: buffer_store_dwordx2 [[REG]]
+define void @add_inline_imm_inv_2pi_f64(double addrspace(1)* %out, double %x) {
+  %y = fadd double %x, 0x3fc45f306dc9c882
+  store double %y, double addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}add_m_inv_2pi_f64:
+; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0x6dc9c882
+; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbfc45f30
+; GCN: v_add_f64 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+define void @add_m_inv_2pi_f64(double addrspace(1)* %out, double %x) {
+  %y = fadd double %x, 0xbfc45f306dc9c882
+  store double %y, double addrspace(1)* %out
+  ret void
+}
 
 ; GCN-LABEL: {{^}}add_inline_imm_1_f64:
 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
 ; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 1{{$}}
 ; GCN: buffer_store_dwordx2 [[REG]]
 define void @add_inline_imm_1_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0x0000000000000001

 ; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
 ; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xc0100000
 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
 define void @store_inline_imm_m_4.0_f64(double addrspace(1)* %out) {
   store double -4.0, double addrspace(1)* %out
   ret void
 }
 
+; GCN-LABEL: {{^}}store_inv_2pi_f64:
+; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0x6dc9c882
+; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3fc45f30
+; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+define void @store_inv_2pi_f64(double addrspace(1)* %out) {
+  store double 0x3fc45f306dc9c882, double addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}store_inline_imm_m_inv_2pi_f64:
+; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0x6dc9c882
+; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbfc45f30
+; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
+define void @store_inline_imm_m_inv_2pi_f64(double addrspace(1)* %out) {
+  store double 0xbfc45f306dc9c882, double addrspace(1)* %out
+  ret void
+}
+
 ; GCN-LABEL: {{^}}store_literal_imm_f64:
 ; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
 ; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x40b00000
 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
 define void @store_literal_imm_f64(double addrspace(1)* %out) {
   store double 4096.0, double addrspace(1)* %out
   ret void
 }