[AMDGPU] Choose VMCNT, EXPCNT, LGKMCNT masks and shifts based on the isa version

[kzhuravl]

I am also planning to introduce 2 new functions for encoding/decoding *CNTs instead of doing pretty much the same math in a few different places, but in a separate patch

[nhaehnle]

LGTM

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Support/MathExtras.h"
 
 using namespace llvm;
+using namespace llvm::AMDGPU;
 
 namespace {
 
 class AMDGPUAsmParser;
 struct OptionalOperand;
 
 enum RegisterKind { IS_UNKNOWN, IS_VGPR, IS_SGPR, IS_TTMP, IS_SPECIAL };
 
bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
 
   Parser.Lex();
   if (getLexer().is(AsmToken::Amp) || getLexer().is(AsmToken::Comma))
     Parser.Lex();
 
   int CntShift;
   int CntMask;
 
+  IsaVersion IV = getIsaVersion(getSTI().getFeatureBits());
   if (CntName == "vmcnt") {
-    CntMask = 0xf;
-    CntShift = 0;
+    CntMask = getVmcntMask(IV);
+    CntShift = getVmcntShift(IV);
   } else if (CntName == "expcnt") {
-    CntMask = 0x7;
-    CntShift = 4;
+    CntMask = getExpcntMask(IV);
+    CntShift = getExpcntShift(IV);
   } else if (CntName == "lgkmcnt") {
-    CntMask = 0xf;
-    CntShift = 8;
+    CntMask = getLgkmcntMask(IV);
+    CntShift = getLgkmcntShift(IV);
   } else {
     return true;
   }
 
   IntVal &= ~(CntMask << CntShift);
   IntVal |= (CntVal << CntShift);
   return false;
 }

llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 // \file
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUInstPrinter.h"
-#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "SIDefines.h"
+#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "Utils/AMDGPUAsmUtils.h"
+#include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 
 #include <string>
 
 using namespace llvm;
+using namespace llvm::AMDGPU;
 
 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
                                   StringRef Annot, const MCSubtargetInfo &STI) {
   OS.flush();
   printInstruction(MI, STI, OS);
   printAnnotation(OS, Annot);
 }
 
do {
     }
   } while (0);
   O << SImm16; // Unknown simm16 code.
 }
 
 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
                                       const MCSubtargetInfo &STI,
                                       raw_ostream &O) {
+  IsaVersion IV = getIsaVersion(STI.getFeatureBits());
+
   unsigned SImm16 = MI->getOperand(OpNo).getImm();
-  unsigned Vmcnt = SImm16 & 0xF;
-  unsigned Expcnt = (SImm16 >> 4) & 0x7;
-  unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
+  unsigned Vmcnt = (SImm16 >> getVmcntShift(IV)) & getVmcntMask(IV);
+  unsigned Expcnt = (SImm16 >> getExpcntShift(IV)) & getExpcntMask(IV);
+  unsigned Lgkmcnt = (SImm16 >> getLgkmcntShift(IV)) & getLgkmcntMask(IV);
 
   bool NeedSpace = false;
 
   if (Vmcnt != 0xF) {
     O << "vmcnt(" << Vmcnt << ')';
     NeedSpace = true;
   }
 

llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPU.h"
 #include "AMDGPUSubtarget.h"
 #include "SIDefines.h"
 #include "SIInstrInfo.h"
 #include "SIMachineFunctionInfo.h"
+#include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 
 #define DEBUG_TYPE "si-insert-waits"
 
 using namespace llvm;
+using namespace llvm::AMDGPU;
 
 namespace {
 
 /// \brief One variable for each of the hardware counters
 typedef union {
   struct {
     unsigned VM;
     unsigned EXP;

 
 class SIInsertWaits : public MachineFunctionPass {
 
 private:
   const SISubtarget *ST;
   const SIInstrInfo *TII;
   const SIRegisterInfo *TRI;
   const MachineRegisterInfo *MRI;
+  IsaVersion IV;
 
   /// \brief Constant hardware limits
   static const Counters WaitCounts;
 
   /// \brief Constant zero value
   static const Counters ZeroCounts;
 
   /// \brief Counter values we have already waited on.
if (!NeedWait)
     return false;
 
   // Reset EXP_CNT instruction types
   if (Counts.Named.EXP == 0)
     ExpInstrTypesSeen = 0;
 
   // Build the wait instruction
   BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
-          .addImm((Counts.Named.VM & 0xF) |
-                  ((Counts.Named.EXP & 0x7) << 4) |
-                  ((Counts.Named.LGKM & 0xF) << 8));
+    .addImm(((Counts.Named.VM & getVmcntMask(IV)) << getVmcntShift(IV)) |
+            ((Counts.Named.EXP & getExpcntMask(IV)) << getExpcntShift(IV)) |
+            ((Counts.Named.LGKM & getLgkmcntMask(IV)) << getLgkmcntShift(IV)));
 
   LastOpcodeType = OTHER;
   LastInstWritesM0 = false;
   return true;
 }
 
 /// \brief helper function for handleOperands
 static void increaseCounters(Counters &Dst, const Counters &Src) {

 }
 
 void SIInsertWaits::handleExistingWait(MachineBasicBlock::iterator I) {
   assert(I->getOpcode() == AMDGPU::S_WAITCNT);
 
   unsigned Imm = I->getOperand(0).getImm();
   Counters Counts, WaitOn;
 
-  Counts.Named.VM = Imm & 0xF;
-  Counts.Named.EXP = (Imm >> 4) & 0x7;
-  Counts.Named.LGKM = (Imm >> 8) & 0xF;
+  Counts.Named.VM = (Imm >> getVmcntShift(IV)) & getVmcntMask(IV);
+  Counts.Named.EXP = (Imm >> getExpcntShift(IV)) & getExpcntMask(IV);
+  Counts.Named.LGKM = (Imm >> getLgkmcntShift(IV)) & getLgkmcntMask(IV);
 
   for (unsigned i = 0; i < 3; ++i) {
     if (Counts.Array[i] <= LastIssued.Array[i])
       WaitOn.Array[i] = LastIssued.Array[i] - Counts.Array[i];
     else
       WaitOn.Array[i] = 0;
   }
 

 // around other non-memory instructions.
 bool SIInsertWaits::runOnMachineFunction(MachineFunction &MF) {
   bool Changes = false;
 
   ST = &MF.getSubtarget<SISubtarget>();
   TII = ST->getInstrInfo();
   TRI = &TII->getRegisterInfo();
   MRI = &MF.getRegInfo();
+  IV = getIsaVersion(ST->getFeatureBits());
 
   WaitedOn = ZeroCounts;
   DelayedWaitOn = ZeroCounts;
   LastIssued = ZeroCounts;
   LastOpcodeType = OTHER;
   LastInstWritesM0 = false;
   ReturnsVoid = MF.getInfo<SIMachineFunctionInfo>()->returnsVoid();
 

llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 /// \returns \p Default and emits error if one of the requested values cannot be
 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
 /// not present.
 std::pair<int, int> getIntegerPairAttribute(const Function &F,
                                             StringRef Name,
                                             std::pair<int, int> Default,
                                             bool OnlyFirstRequired = false);
 
+/// \returns VMCNT bit mask for given isa \p Version.
+unsigned getVmcntMask(IsaVersion Version);
+
+/// \returns VMCNT bit shift for given isa \p Version.
+unsigned getVmcntShift(IsaVersion Version);
+
+/// \returns EXPCNT bit mask for given isa \p Version.
+unsigned getExpcntMask(IsaVersion Version);
+
+/// \returns EXPCNT bit shift for given isa \p Version.
+unsigned getExpcntShift(IsaVersion Version);
+
+/// \returns LGKMCNT bit mask for given isa \p Version.
+unsigned getLgkmcntMask(IsaVersion Version);
+
+/// \returns LGKMCNT bit shift for given isa \p Version.
+unsigned getLgkmcntShift(IsaVersion Version);
+
 unsigned getInitialPSInputAddr(const Function &F);
 
 bool isShader(CallingConv::ID cc);
 bool isCompute(CallingConv::ID cc);
 
 bool isSI(const MCSubtargetInfo &STI);
 bool isCI(const MCSubtargetInfo &STI);
 bool isVI(const MCSubtargetInfo &STI);

llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

if (!OnlyFirstRequired || Strs.second.trim().size()) {
       Ctx.emitError("can't parse second integer attribute " + Name);
       return Default;
     }
   }
 
   return Ints;
 }
 
+unsigned getVmcntMask(IsaVersion Version) {
+  return 0xf;
+}
+
+unsigned getVmcntShift(IsaVersion Version) {
+  return 0;
+}
+
+unsigned getExpcntMask(IsaVersion Version) {
+  return 0x7;
+}
+
+unsigned getExpcntShift(IsaVersion Version) {
+  return 4;
+}
+
+unsigned getLgkmcntMask(IsaVersion Version) {
+  return 0xf;
+}
+
+unsigned getLgkmcntShift(IsaVersion Version) {
+  return 8;
+}
+
 unsigned getInitialPSInputAddr(const Function &F) {
   return getIntegerAttribute(F, "InitialPSInputAddr", 0);
 }
 
 bool isShader(CallingConv::ID cc) {
   switch(cc) {
     case CallingConv::AMDGPU_VS:
     case CallingConv::AMDGPU_GS: