AMDGPU/SI: Make sure llvm.amdgcn.implicitarg.ptr() is 8-byte aligned for HSA

[arsenm]

LGTM

lib/Target/AMDGPU/GCNSchedStrategy.cpp

37

This looks accidentally included

[• tstellarAMD]

Remove unrelated change.

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
   } else {
     VirtualRegister = MRI.getLiveInVirtReg(Reg);
   }
   return DAG.getRegister(VirtualRegister, VT);
 }
 
 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
     const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const {
-  uint64_t ArgOffset = alignTo(MFI->getABIArgOffset(), 4);
+  unsigned Alignment = Subtarget->getAlignmentForImplicitArgPtr();
+  uint64_t ArgOffset = alignTo(MFI->getABIArgOffset(), Alignment);
   switch (Param) {
   case GRID_DIM:
     return ArgOffset;
   case GRID_OFFSET:
     return ArgOffset + 4;
   }
   llvm_unreachable("unexpected implicit parameter type");
 }

lib/Target/AMDGPU/AMDGPUSubtarget.h

public:
   }
 
   /// \brief Returns the offset in bytes from the start of the input buffer
   ///        of the first explicit kernel argument.
   unsigned getExplicitKernelArgOffset() const {
     return isAmdHsaOS() ? 0 : 36;
   }
 
+  unsigned getAlignmentForImplicitArgPtr() const {
+    return isAmdHsaOS() ? 8 : 4;
+  }
+
   unsigned getStackAlignment() const {
     // Scratch is allocated in 256 dword per wave blocks.
     return 4 * 256 / getWavefrontSize();
   }
 
   bool enableMachineScheduler() const override {
     return true;
   }

lib/Target/AMDGPU/GCNSchedStrategy.cpp

 
 static unsigned getMaxWaves(unsigned SGPRs, unsigned VGPRs,
                             const MachineFunction &MF) {
 
   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
   unsigned MinRegOccupancy = std::min(ST.getOccupancyWithNumSGPRs(SGPRs),
                                       ST.getOccupancyWithNumVGPRs(VGPRs));
+  return MinRegOccupancy;
   return std::min(MinRegOccupancy,
                   ST.getOccupancyWithLocalMemSize(MFI->getLDSSize()));
 }
 
 void GCNMaxOccupancySchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU,
                                      bool AtTop, const RegPressureTracker &RPTracker,
                                      const SIRegisterInfo *SRI,
                                      int SGPRPressure,

test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll

define void @test_implicit(i32 addrspace(1)* %out) #1 {
   %gep = getelementptr i32, i32 addrspace(2)* %header.ptr, i64 10
   %value = load i32, i32 addrspace(2)* %gep
   store i32 %value, i32 addrspace(1)* %out
   ret void
 }
 
 ; ALL-LABEL: {{^}}test_implicit_alignment
 ; MESA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
-; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3
+; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
 ; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]
 ; MESA: buffer_store_dword [[V_VAL]]
 ; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]
 define void @test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #1 {
   %implicitarg.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr()
   %arg.ptr = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)*
   %val = load i32, i32 addrspace(2)* %arg.ptr
   store i32 %val, i32 addrspace(1)* %out
   ret void
 }
 
 declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #0
 declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #0
 
 attributes #0 = { nounwind readnone }
 attributes #1 = { nounwind }