AMDGPU: Remove code I think is dead

[arsenm]

Summary

As far as I can tell, resolveFrameIndex is supposed to be
called with a legal offset, so inserting an add shouldn't be
necessary.

[nhaehnle]

I'm not deep enough into this code to really say what's expected, but I remember changing something there because the ADD path _was_ triggered (although I'm not sure whether it was here or in materializeFrameBaseRegister or both). The offending shader is attached to the bug report at https://bugs.freedesktop.org/show_bug.cgi?id=96602, perhaps you could check if that compiles with this change?

[arsenm]

In D24285#537988, @nhaehnle wrote:

I'm not deep enough into this code to really say what's expected, but I remember changing something there because the ADD path _was_ triggered (although I'm not sure whether it was here or in materializeFrameBaseRegister or both). The offending shader is attached to the bug report at https://bugs.freedesktop.org/show_bug.cgi?id=96602, perhaps you could check if that compiles with this change?

That compiles (as well as the testcase you committed with that fix)

[arsenm]

r281372

lib/Target/AMDGPU/SIRegisterInfo.cpp

#endif
 
   MachineOperand *FIOp = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
   assert(FIOp && FIOp->isFI() && "frame index must be address operand");
 
   assert(TII->isMUBUF(MI));
 
   MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset);
   int64_t NewOffset = OffsetOp->getImm() + Offset;
-  if (isUInt<12>(NewOffset)) {
-    // If we have a legal offset, fold it directly into the instruction.
-    FIOp->ChangeToRegister(BaseReg, false);
-    OffsetOp->setImm(NewOffset);
-    return;
-  }
-
-  // The offset is not legal, so we must insert an add of the offset.
-  MachineRegisterInfo &MRI = MF->getRegInfo();
-  unsigned NewReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
-  DebugLoc DL = MI.getDebugLoc();
-
-  assert(Offset != 0 && "Non-zero offset expected");
-
-  unsigned UnusedCarry = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
-  unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
-
-  // In the case the instruction already had an immediate offset, here only
-  // the requested new offset is added because we are leaving the original
-  // immediate in place.
-  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
-    .addImm(Offset);
-  BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ADD_I32_e64), NewReg)
-    .addReg(UnusedCarry, RegState::Define | RegState::Dead)
-    .addReg(OffsetReg, RegState::Kill)
-    .addReg(BaseReg);
-
-  FIOp->ChangeToRegister(NewReg, false);
+  assert(isUInt<12>(NewOffset) && "offset should be legal");
+
 }
 
 bool SIRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
                                         unsigned BaseReg,
                                         int64_t Offset) const {
   return SIInstrInfo::isMUBUF(*MI) && isUInt<12>(Offset);
 }