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AMDGPU: Fix spilling of m0
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Authored by arsenm on Sep 1 2016, 11:12 AM.

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Reviewers
tstellarAMD
Summary

readlane/writelane do not support using m0 as the output/input.
Constrain the register class of spill vregs to try to avoid this,
but also handle spilling of the physreg when necessary by inserting
an additional copy to a normal SGPR.

Diff Detail

Event Timeline

arsenm updated this revision to Diff 70030.Sep 1 2016, 11:12 AM
arsenm retitled this revision from to AMDGPU: Fix spilling of m0.
arsenm updated this object.
arsenm added a reviewer: tstellarAMD.
arsenm added a subscriber: llvm-commits.
tstellarAMD accepted this revision.Sep 1 2016, 2:03 PM
tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Sep 1 2016, 2:03 PM
arsenm closed this revision.Sep 3 2016, 12:06 AM

r280584