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AMDGPU: Fix sched type for branches
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Authored by arsenm on Aug 17 2016, 11:55 AM.

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• tstellarAMD

arsenm retitled this revision from to AMDGPU: Fix sched type for branches.

arsenm updated this object.

arsenm added a subscriber: llvm-commits.

LGTM.

This revision is now accepted and ready to land.Aug 26 2016, 5:36 PM

r279900

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lib/

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AMDGPU/

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	def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm",			def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm",
	[(AMDGPUendpgm)]> {			[(AMDGPUendpgm)]> {
	let simm16 = 0;			let simm16 = 0;
	let isBarrier = 1;			let isBarrier = 1;
	let isReturn = 1;			let isReturn = 1;
	}			}

	let isBranch = 1 in {			let isBranch = 1, SchedRW = [WriteBranch] in {
	def S_BRANCH : SOPP <			def S_BRANCH : SOPP <
	0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16",			0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16",
	[(br bb:$simm16)]> {			[(br bb:$simm16)]> {
	let isBarrier = 1;			let isBarrier = 1;
	}			}

	let Uses = [SCC] in {			let Uses = [SCC] in {
	def S_CBRANCH_SCC0 : SOPP <			def S_CBRANCH_SCC0 : SOPP <
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