[mips] interAptiv based generic schedule model

[sdardis]

Summary

This scheduler describes a processor which covers all MIPS ISAs based
around the interAptiv and P5600 timings.

[dsanders]

LGTM with the ResourceCycles corrected, a couple other minor changes, and an explanation for the dsr-fixed-objects.ll change

lib/Target/Mips/Mips.td

194 ↗

(On Diff #68168)

If MipsGenericItineraries is no longer used can we delete it (in a follow-up patch)?

lib/Target/Mips/MipsScheduleGeneric.td

202–203 ↗

(On Diff #68168)

Could you uncomment these and add II_MFHC0 to the microMIPSR6 definitions? We don't seem to have MFHC0 for the other ISA's it exists for.

260 ↗

(On Diff #68168)

Indentation

349–380 ↗

(On Diff #68168)

I doubt these are working as intended since there are two ResourceCycles elements but only one resource and ResourceCycles are paired up with the resources. I think the current definition for GenericWriteFPUSqrtD is saying that it consumes the GenericFPUDivSqrt resource for a single cycle which is equivalent to a fully-pipelined divide path.

I think you need to remove each of the '1' elements since these corresponded with an issue port on the P5600 definitions.

Likewise for GenericDiv other places where ResourceCycles is set.

436 ↗

(On Diff #68168)

Indentation

440 ↗

(On Diff #68168)

Indentation

test/DebugInfo/Mips/dsr-fixed-objects.ll

32 ↗

(On Diff #68168)

Could you explain why this changed?

[sdardis]

test/DebugInfo/Mips/dsr-fixed-objects.ll

32 ↗

(On Diff #68168)

This change occurred as an instruction moved before a label.

[dsanders]

test/DebugInfo/Mips/dsr-fixed-objects.ll

32 ↗

(On Diff #68168)

Ok, thanks.

[sdardis]

Addressed review comments.

[tfiala]

Our LLDB Xcode build seems to be failing on not finding MipsScheduleGeneric.td:

[1776/2600] Building CXX object lib/Target/Lanai/CMakeFiles/LLVMLanaiCodeGen.dir/LanaiDelaySlotFiller.cpp.o
FAILED: cd /Volumes/Data/src/lldb-llvm.org/lldb/llvm-build/Release+Asserts/x86_64/lib/Target/Mips && /Volumes/Data/src/lldb-llvm.org/lldb/llvm-build/Release+Asserts/x86_64/bin/llvm-tblgen -gen-fast-isel -I /Volumes/Data/src/lldb-llvm.org/lldb/llvm/lib/Target/Mips -I /Volumes/Data/src/lldb-llvm.org/lldb/llvm/lib/Target -I /Volumes/Data/src/lldb-llvm.org/lldb/llvm/include /Volumes/Data/src/lldb-llvm.org/lldb/llvm/lib/Target/Mips/Mips.td -o /Volumes/Data/src/lldb-llvm.org/lldb/llvm-build/Release+Asserts/x86_64/lib/Target/Mips/MipsGenFastISel.inc.tmp
/Volumes/Data/src/lldb-llvm.org/lldb/llvm/lib/Target/Mips/Mips.td:62:9: error: Could not find include file 'MipsScheduleGeneric.td'
include "MipsScheduleGeneric.td"
        ^
/Volumes/Data/src/lldb-llvm.org/lldb/llvm/lib/Target/Mips/Mips.td:62:9: error: Unexpected input at top level
include "MipsScheduleGeneric.td"
        ^
FAILED: cd /Volumes/Data/src/lldb-llvm.org/lldb/llvm-build/Release+Asserts/x86_64/lib/Target/Mips && /Volumes/Data/src/lldb-llvm.org/lldb/llvm-build/Release+Asserts/x86_64/bin/llvm-tblgen -gen-asm-matcher -I /Volumes/Data/src/lldb-llvm.org/lldb/llvm/lib/Target/Mips -I /Volumes/Data/src/lldb-llvm.org/lldb/llvm/lib/Target -I /Volumes/Data/src/lldb-llvm.org/lldb/llvm/include /Volumes/Data/src/lldb-llvm.org/lldb/llvm/lib/Target/Mips/Mips.td -o /Volumes/Data/src/lldb-llvm.org/lldb/llvm-build/Release+Asserts/x86_64/lib/Target/Mips/MipsGenAsmMatcher.inc.tmp
/Volumes/Data/src/lldb-llvm.org/lldb/llvm/lib/Target/Mips/Mips.td:62:9: error: Could not find include file 'MipsScheduleGeneric.td'
include "MipsScheduleGeneric.td"
        ^
/Volumes/Data/src/lldb-llvm.org/lldb/llvm/lib/Target/Mips/Mips.td:62:9: error: Unexpected input at top level
include "MipsScheduleGeneric.td"
        ^
ninja: build stopped: subcommand failed.

This might just need a clean build, looking into that now.

[sdardis]

I included that missing file in rL280377 . Sorry about the breakage.

[tfiala]

In D23551#531537, @sdardis wrote:

I included that missing file in rL280377 . Sorry about the breakage.

That seems to have fixed it, thanks!

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

 
 class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd,
                                            II_MTC0>;
 class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
                                            II_MTC1, bitconvert>, HARDFLOAT;
 class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd,
                                            II_MTC2>;
 class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd,
-                                            II_MTC0>;
+                                            II_MTHC0>;
 class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd,
                                                    GPR32Opnd, II_MTC1>,
                             HARDFLOAT, FGR_32;
 class MTHC1_D64_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", FGR64Opnd,
                                                    GPR32Opnd, II_MTC1>,
                             HARDFLOAT, FGR_64;
 class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd,
                                             II_MTC2>;

 }
 class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd,
                                            II_MFC0>;
 class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
                                            II_MFC1, bitconvert>, HARDFLOAT;
 class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd,
                                            II_MFC2>;
 class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd,
-                                            II_MFC0>;
+                                            II_MFHC0>;
 class MFHC1_D32_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd,
                                                 II_MFHC1>, HARDFLOAT, FGR_32;
 class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, FGR64Opnd,
                                                 II_MFHC1>, HARDFLOAT, FGR_64;
 class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd,
                                             II_MFC2>;
 
 class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {

llvm/trunk/lib/Target/Mips/Mips.td

 
 include "MipsRegisterInfo.td"
 include "MipsSchedule.td"
 include "MipsInstrInfo.td"
 include "MipsCallingConv.td"
 
 // Avoid forward declaration issues.
 include "MipsScheduleP5600.td"
+include "MipsScheduleGeneric.td"
 
 def MipsInstrInfo : InstrInfo;
 
 //===----------------------------------------------------------------------===//
 // Mips Subtarget features                                                    //
 //===----------------------------------------------------------------------===//
 
 def FeatureNoABICalls  : SubtargetFeature<"noabicalls", "NoABICalls", "true",

 // Mips processors supported.
 //===----------------------------------------------------------------------===//
 
 def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
                                  "MipsSubtarget::CPU::P5600",
                                  "The P5600 Processor", [FeatureMips32r5]>;
 
 class Proc<string Name, list<SubtargetFeature> Features>
- : Processor<Name, MipsGenericItineraries, Features>;
+ : ProcessorModel<Name, MipsGenericModel, Features>;
 
 def : Proc<"mips1", [FeatureMips1]>;
 def : Proc<"mips2", [FeatureMips2]>;
 def : Proc<"mips32", [FeatureMips32]>;
 def : Proc<"mips32r2", [FeatureMips32r2]>;
 def : Proc<"mips32r3", [FeatureMips32r3]>;
 def : Proc<"mips32r5", [FeatureMips32r5]>;
 def : Proc<"mips32r6", [FeatureMips32r6]>;

llvm/trunk/lib/Target/Mips/MipsSchedule.td

 def II_MAX_S            : InstrItinClass;
 def II_MAXA_D           : InstrItinClass;
 def II_MAXA_S           : InstrItinClass;
 def II_MIN_D            : InstrItinClass;
 def II_MIN_S            : InstrItinClass;
 def II_MINA_D           : InstrItinClass;
 def II_MINA_S           : InstrItinClass;
 def II_MFC0             : InstrItinClass;
+def II_MFHC0            : InstrItinClass;
 def II_MFC1             : InstrItinClass;
 def II_MFHC1            : InstrItinClass;
 def II_MFC2             : InstrItinClass;
 def II_MFHI_MFLO        : InstrItinClass; // mfhi and mflo
 def II_MOD              : InstrItinClass;
 def II_MODU             : InstrItinClass;
 def II_MOVE             : InstrItinClass;
 def II_MOVF             : InstrItinClass;

 def II_MOV_S            : InstrItinClass;
 def II_MSUB             : InstrItinClass;
 def II_MSUBU            : InstrItinClass;
 def II_MSUB_D           : InstrItinClass;
 def II_MSUB_S           : InstrItinClass;
 def II_MSUBF_D          : InstrItinClass;
 def II_MSUBF_S          : InstrItinClass;
 def II_MTC0             : InstrItinClass;
+def II_MTHC0            : InstrItinClass;
 def II_MTC1             : InstrItinClass;
 def II_MTHC1            : InstrItinClass;
 def II_MTC2             : InstrItinClass;
 def II_MTHI_MTLO        : InstrItinClass; // mthi and mtlo
 def II_MUL              : InstrItinClass;
 def II_MUH              : InstrItinClass;
 def II_MUHU             : InstrItinClass;
 def II_MULU             : InstrItinClass;
def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
   InstrItinData<II_SUXC1           , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_DMFC0           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_DMFC1           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_DMFC2           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_DMTC0           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_DMTC1           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_DMTC2           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MFC0            , [InstrStage<2,  [ALU]>]>,
+  InstrItinData<II_MFHC0           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MFC1            , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MFC2            , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MTC0            , [InstrStage<2,  [ALU]>]>,
+  InstrItinData<II_MTHC0           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MTC1            , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MTC2            , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MFHC1           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MTHC1           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_CACHE           , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_PREF            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_CACHEE          , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_PREFE           , [InstrStage<1,  [ALU]>]>,

llvm/trunk/test/CodeGen/Mips/biggot.ll

 ; O32: lui $[[R0:[0-9]+]], %got_hi(v0)
 ; O32: addu  $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}}
 ; O32: lw  ${{[0-9]+}}, %got_lo(v0)($[[R1]])
 ; O32: lui $[[R2:[0-9]+]], %call_hi(foo0)
 ; O32: addu  $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
 ; O32: lw  ${{[0-9]+}}, %call_lo(foo0)($[[R3]])
 
 ; N64-LABEL: foo1:
-; N64: lui $[[R0:[0-9]+]], %got_hi(v0)
-; N64: daddu  $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}}
-; N64: lui $[[R2:[0-9]+]], %call_hi(foo0)
-; N64: daddu  $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
-; N64: ld  ${{[0-9]+}}, %got_lo(v0)($[[R1]])
-; N64: ld  ${{[0-9]+}}, %call_lo(foo0)($[[R3]])
+; N64-DAG: lui $[[R0:[0-9]+]], %got_hi(v0)
+; N64-DAG: daddu  $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}}
+; N64-DAG: lui $[[R2:[0-9]+]], %call_hi(foo0)
+; N64-DAG: daddu  $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
+; N64-DAG: ld  ${{[0-9]+}}, %got_lo(v0)($[[R1]])
+; N64-DAG: ld  ${{[0-9]+}}, %call_lo(foo0)($[[R3]])
 
   %0 = load i32, i32* @v0, align 4
   tail call void @foo0(i32 %0) nounwind
   ret void
 }
 
 declare void @foo0(i32)
 

llvm/trunk/test/CodeGen/Mips/divrem.ll

 
 ; ACC64:         div $zero, $4, $5
 ; ACC64-TRAP:    teq $5, $zero, 7
 ; NOCHECK-NOT:   teq
 ; ACC64:         mflo $2
 ; ACC64:         mfhi $[[R0:[0-9]+]]
 ; ACC64:         sw $[[R0]], 0(${{[0-9]+}})
 
-; GPR32-DAG:     div $2, $4, $5
-; GPR32-TRAP:    teq $5, $zero, 7
-; NOCHECK-NOT:   teq
 ; GPR32-DAG:     mod $[[R0:[0-9]+]], $4, $5
 ; GPR32-TRAP:    teq $5, $zero, 7
+; NOCHECK-NOT:   teq
 ; GPR32:         sw $[[R0]], 0(${{[0-9]+}})
+; GPR32-DAG:     div $2, $4, $5
+; GPR32-TRAP:    teq $5, $zero, 7
 
-; GPR64-DAG:     div $2, $4, $5
-; GPR64-TRAP:    teq $5, $zero, 7
-; NOCHECK-NOT:   teq
 ; GPR64-DAG:     mod $[[R0:[0-9]+]], $4, $5
 ; GPR64-TRAP:    teq $5, $zero, 7
 ; NOCHECK-NOT:   teq
 ; GPR64:         sw $[[R0]], 0(${{[0-9]+}})
+; GPR64-DAG:     div $2, $4, $5
+; GPR64-TRAP:    teq $5, $zero, 7
+; NOCHECK-NOT:   teq
 
 ; ALL: .end sdivrem1
 
   %rem = srem i32 %a0, %a1
   store i32 %rem, i32* %r, align 4
   %div = sdiv i32 %a0, %a1
   ret i32 %div
 }

 
 ; ACC64:         divu $zero, $4, $5
 ; ACC64-TRAP:    teq $5, $zero, 7
 ; NOCHECK-NOT:   teq
 ; ACC64:         mflo $2
 ; ACC64:         mfhi $[[R0:[0-9]+]]
 ; ACC64:         sw $[[R0]], 0(${{[0-9]+}})
 
-; GPR32-DAG:     divu $2, $4, $5
+; GPR32-DAG:     modu $[[R0:[0-9]+]], $4, $5
 ; GPR32-TRAP:    teq $5, $zero, 7
+; GPR32:         sw $[[R0]], 0(${{[0-9]+}})
 ; NOCHECK-NOT:   teq
-; GPR32-DAG:     modu $[[R0:[0-9]+]], $4, $5
+; GPR32-DAG:     divu $2, $4, $5
 ; GPR32-TRAP:    teq $5, $zero, 7
 ; NOCHECK-NOT:   teq
-; GPR32:         sw $[[R0]], 0(${{[0-9]+}})
 
-; GPR64-DAG:     divu $2, $4, $5
-; GPR64-TRAP:    teq $5, $zero, 7
-; NOCHECK-NOT:   teq
 ; GPR64-DAG:     modu $[[R0:[0-9]+]], $4, $5
 ; GPR64-TRAP:    teq $5, $zero, 7
 ; NOCHECK-NOT:   teq
 ; GPR64:         sw $[[R0]], 0(${{[0-9]+}})
+; GPR64-DAG:     divu $2, $4, $5
+; GPR64-TRAP:    teq $5, $zero, 7
+; NOCHECK-NOT:   teq
 
 ; ALL: .end udivrem1
 
   %rem = urem i32 %a0, %a1
   store i32 %rem, i32* %r, align 4
   %div = udiv i32 %a0, %a1
   ret i32 %div
 }

 
 ; ACC64:         ddiv $zero, $4, $5
 ; ACC64-TRAP:    teq $5, $zero, 7
 ; NOCHECK-NOT:   teq
 ; ACC64:         mflo $2
 ; ACC64:         mfhi $[[R0:[0-9]+]]
 ; ACC64:         sd $[[R0]], 0(${{[0-9]+}})
 
-; GPR64-DAG:     ddiv $2, $4, $5
+; GPR64-DAG:     dmod $[[R0:[0-9]+]], $4, $5
 ; GPR64-TRAP:    teq $5, $zero, 7
 ; NOCHECK-NOT:   teq
+; GPR64:         sd $[[R0]], 0(${{[0-9]+}})
 
-; GPR64-DAG:     dmod $[[R0:[0-9]+]], $4, $5
+; GPR64-DAG:     ddiv $2, $4, $5
 ; GPR64-TRAP:    teq $5, $zero, 7
 ; NOCHECK-NOT:   teq
-; GPR64:         sd $[[R0]], 0(${{[0-9]+}})
 
 ; ALL: .end sdivrem2
 
   %rem = srem i64 %a0, %a1
   store i64 %rem, i64* %r, align 8
   %div = sdiv i64 %a0, %a1
   ret i64 %div
 }

 
 ; ACC64:         ddivu $zero, $4, $5
 ; ACC64-TRAP:    teq $5, $zero, 7
 ; NOCHECK-NOT:   teq
 ; ACC64:         mflo $2
 ; ACC64:         mfhi $[[R0:[0-9]+]]
 ; ACC64:         sd $[[R0]], 0(${{[0-9]+}})
 
-; GPR64-DAG:     ddivu $2, $4, $5
+; GPR64:         dmodu $[[R0:[0-9]+]], $4, $5
 ; GPR64-TRAP:    teq $5, $zero, 7
 ; NOCHECK-NOT:   teq
+; GPR64:         sd $[[R0]], 0(${{[0-9]+}})
 
-; GPR64:         dmodu $[[R0:[0-9]+]], $4, $5
+; GPR64-DAG:     ddivu $2, $4, $5
 ; GPR64-TRAP:    teq $5, $zero, 7
 ; NOCHECK-NOT:   teq
-; GPR64:         sd $[[R0]], 0(${{[0-9]+}})
 
 ; ALL: .end udivrem2
 
   %rem = urem i64 %a0, %a1
   store i64 %rem, i64* %r, align 8
   %div = udiv i64 %a0, %a1
   ret i64 %div
 }

llvm/trunk/test/CodeGen/Mips/fcopysign-f32-f64.ll

; 64R2: mtc1 $[[INS]], $f0
   %call = tail call float @copysignf(float %add, float %conv) nounwind readnone
   ret float %call
 }
 
 define double @func3(double %d, float %f) nounwind readnone {
 entry:
 ; ALL-LABEL: func3:
 
-; 64-DAG: mfc1    $[[MFC:[0-9]+]], $f13
-; 64-DAG: srl     $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
-; 64:     dsll    $[[DSLL:[0-9]+]], $[[SRL]], 63
-; 64-DAG: daddiu  $[[R1:[0-9]+]], $zero, 1
-; 64-DAG: dsll    $[[R2:[0-9]+]], $[[R1]], 63
-; 64-DAG: daddiu  $[[R3:[0-9]+]], $[[R2]], -1
-; 64-DAG: dmfc1   $[[R0:[0-9]+]], ${{.*}}
+; 64:     dmfc1   $[[R0:[0-9]+]], ${{.*}}
+; 64:     daddiu  $[[R1:[0-9]+]], $zero, 1
+; 64:     dsll    $[[R2:[0-9]+]], $[[R1]], 63
+; 64:     daddiu  $[[R3:[0-9]+]], $[[R2]], -1
 ; 64:     and     $[[AND0:[0-9]+]], $[[R0]], $[[R3]]
+; 64:     mfc1    $[[MFC:[0-9]+]], $f13
+; 64:     srl     $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
+; 64:     dsll    $[[DSLL:[0-9]+]], $[[SRL]], 63
 ; 64:     or      $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
 ; 64:     dmtc1   $[[OR]], $f0
 
 ; 64R2: ext   ${{[0-9]+}}, ${{[0-9]+}}, 31, 1
 ; 64R2: dins  $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1
 ; 64R2: dmtc1 $[[INS]], $f0
 
   %add = fadd double %d, 1.000000e+00
   %conv = fpext float %f to double
   %call = tail call double @copysign(double %add, double %conv) nounwind readnone
   ret double %call
 }

llvm/trunk/test/CodeGen/Mips/llvm-ir/add.ll

 ; ALL-LABEL: add_i128:
 
   ; GP32:       lw        $[[T0:[0-9]+]], 28($sp)
   ; GP32:       addu      $[[T1:[0-9]+]], $7, $[[T0]]
   ; GP32:       sltu      $[[T2:[0-9]+]], $[[T1]], $[[T0]]
   ; GP32:       lw        $[[T3:[0-9]+]], 24($sp)
   ; GP32:       addu      $[[T4:[0-9]+]], $[[T2]], $[[T3]]
   ; GP32:       addu      $[[T5:[0-9]+]], $6, $[[T4]]
-  ; GP32:       lw        $[[T6:[0-9]+]], 16($sp)
+  ; GP32:       sltu      $[[T6:[0-9]+]], $[[T5]], $[[T3]]
   ; GP32:       lw        $[[T7:[0-9]+]], 20($sp)
-  ; GP32:       sltu      $[[T8:[0-9]+]], $[[T5]], $[[T3]]
-  ; GP32:       addu      $[[T9:[0-9]+]], $[[T8]], $[[T7]]
+  ; GP32:       addu      $[[T8:[0-9]+]], $[[T6]], $[[T7]]
+  ; GP32:       lw        $[[T9:[0-9]+]], 16($sp)
   ; GP32:       addu      $3, $5, $[[T8]]
   ; GP32:       sltu      $[[T10:[0-9]+]], $3, $[[T7]]
-  ; GP32:       addu      $[[T11:[0-9]+]], $[[T10]], $[[T6]]
+  ; GP32:       addu      $[[T11:[0-9]+]], $[[T10]], $[[T9]]
   ; GP32:       addu      $2, $4, $[[T11]]
   ; GP32:       move      $4, $[[T5]]
   ; GP32:       move      $5, $[[T1]]
 
   ; GP64:       daddu     $3, $5, $7
   ; GP64:       sltu      $[[T0:[0-9]+]], $3, $7
   ; GP64:       daddu     $[[T1:[0-9]+]], $[[T0]], $6
   ; GP64:       daddu     $2, $4, $[[T1]]
 
   ; MM32:       lw        $[[T0:[0-9]+]], 28($sp)
   ; MM32:       addu      $[[T1:[0-9]+]], $7, $[[T0]]
   ; MM32:       sltu      $[[T2:[0-9]+]], $[[T1]], $[[T0]]
   ; MM32:       lw        $[[T3:[0-9]+]], 24($sp)
   ; MM32:       addu      $[[T4:[0-9]+]], $[[T2]], $[[T3]]
   ; MM32:       addu      $[[T5:[0-9]+]], $6, $[[T4]]
-  ; MM32:       lw        $[[T6:[0-9]+]], 16($sp)
+  ; MM32:       sltu      $[[T6:[0-9]+]], $[[T5]], $[[T3]]
   ; MM32:       lw        $[[T7:[0-9]+]], 20($sp)
-  ; MM32:       sltu      $[[T8:[0-9]+]], $[[T5]], $[[T3]]
-  ; MM32:       addu      $[[T9:[0-9]+]], $[[T8]], $[[T7]]
-  ; MM32:       addu      $[[T10:[0-9]+]], $5, $[[T9]]
-  ; MM32:       sltu      $[[T11:[0-6]+]], $[[T9]], $[[T7]]
-  ; MM32:       addu      $[[T12:[0-6]+]], $[[T11]], $[[T6]]
+  ; MM32:       addu      $[[T8:[0-9]+]], $[[T6]], $[[T7]]
+  ; MM32:       lw        $[[T9:[0-9]+]], 16($sp)
+  ; MM32:       addu      $[[T10:[0-9]+]], $5, $[[T8]]
+  ; MM32:       sltu      $[[T11:[0-9]+]], $[[T10]], $[[T7]]
+  ; MM32:       addu      $[[T12:[0-9]+]], $[[T11]], $[[T9]]
   ; MM32:       addu      $[[T13:[0-9]+]], $4, $[[T12]]
   ; MM32:       move      $4, $[[T5]]
   ; MM32:       move      $5, $[[T1]]
 
   ; MM64:       daddu     $3, $5, $7
   ; MM64:       sltu      $[[T0:[0-9]+]], $3, $7
   ; MM64:       daddu     $[[T1:[0-9]+]], $[[T0]], $6
   ; MM64:       daddu     $2, $4, $[[T1]]

llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll

; ALL-LABEL: and_i64:
   %r = and i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @and_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: and_i128:
 
-  ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
-  ; GP32:         lw      $[[T1:[0-9]+]], 20($sp)
-  ; GP32:         lw      $[[T2:[0-9]+]], 16($sp)
-  ; GP32:         and     $2, $4, $[[T2]]
-  ; GP32:         and     $3, $5, $[[T1]]
-  ; GP32:         and     $4, $6, $[[T0]]
+  ; GP32:         lw      $[[T0:[0-9]+]], 20($sp)
+  ; GP32:         lw      $[[T1:[0-9]+]], 16($sp)
+  ; GP32:         and     $2, $4, $[[T1]]
+  ; GP32:         and     $3, $5, $[[T0]]
+  ; GP32:         lw      $[[T2:[0-9]+]], 24($sp)
+  ; GP32:         and     $4, $6, $[[T2]]
   ; GP32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; GP32:         and     $5, $7, $[[T3]]
 
   ; GP64:         and     $2, $4, $6
   ; GP64:         and     $3, $5, $7
 
-  ; MM32:         lw      $[[T0:[0-9]+]], 32($sp)
-  ; MM32:         lw      $[[T1:[0-9]+]], 28($sp)
+  ; MM32:         lw      $[[T0:[0-9]+]], 20($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
+  ; MM32:         and16   $[[T1]], $4
+  ; MM32:         and16   $[[T0]], $5
   ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
-  ; MM32:         and16   $[[T2]], $4
-  ; MM32:         and16   $[[T1]], $5
-  ; MM32:         and16   $[[T0]], $6
-  ; MM32:         lw      $[[T3:[0-9]+]], 36($sp)
+  ; MM32:         and16   $[[T2]], $6
+  ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         and16   $[[T3]], $7
 
   ; MM64:         and     $2, $4, $6
   ; MM64:         and     $3, $5, $7
 
   %r = and i128 %a, %b
   ret i128 %r
 }

llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll

; ALL-LABEL: mul_i64:
   ; M2:         mflo    $3
   ; M2:         mfhi    $4
   ; M2:         addu    $[[T2:[0-9]+]], $4, $[[T1]]
   ; M2:         addu    $2, $[[T2]], $[[T0]]
 
   ; 32R1-R5:    multu   $5, $7
   ; 32R1-R5:    mflo    $3
   ; 32R1-R5:    mfhi    $[[T0:[0-9]+]]
-  ; 32R1-R5:    mul     $[[T1:[0-9]+]], $4, $7
-  ; 32R1-R5:    mul     $[[T2:[0-9]+]], $5, $6
-  ; 32R1-R5:    addu    $[[T0]], $[[T0]], $[[T2:[0-9]+]]
-  ; 32R1-R5:    addu    $2, $[[T0]], $[[T1]]
-
+  ; 32R1-R5:    mul     $[[T1:[0-9]+]], $5, $6
+  ; 32R1-R5:    addu    $[[T0]], $[[T0]], $[[T1:[0-9]+]]
+  ; 32R1-R5:    mul     $[[T2:[0-9]+]], $4, $7
+  ; 32R1-R5:    addu    $2, $[[T0]], $[[T2]]
+
+  ; 32R6-DAG:   mul     $[[T0:[0-9]+]], $5, $6
+  ; 32R6:       muhu    $[[T1:[0-9]+]], $5, $7
+  ; 32R6:       addu    $[[T0]], $[[T1]], $[[T0]]
+  ; 32R6-DAG:   mul     $[[T2:[0-9]+]], $4, $7
+  ; 32R6:       addu    $2, $[[T0]], $[[T2]]
   ; 32R6-DAG:   mul     $3, $5, $7
-  ; 32R6-DAG:   mul     $[[T0:[0-9]+]], $4, $7
-  ; 32R6-DAG:   mul     $[[T1:[0-9]+]], $5, $6
-  ; 32R6:       muhu    $[[T2:[0-9]+]], $5, $7
-  ; 32R6:       addu    $[[T1]], $[[T2]], $[[T1]]
-  ; 32R6:       addu    $2, $[[T1]], $[[T0]]
 
   ; M4:         dmult   $4, $5
   ; M4:         mflo    $2
 
   ; 64R1-R5:    dmult   $4, $5
   ; 64R1-R5:    mflo    $2
 
   ; 64R6:       dmul    $2, $4, $5
 
   ; MM32R3:     multu   $[[T0:[0-9]+]], $7
   ; MM32R3:     mflo    $[[T1:[0-9]+]]
   ; MM32R3:     mfhi    $[[T2:[0-9]+]]
-  ; MM32R3:     mul     $[[T3:[0-9]+]], $4, $7
   ; MM32R3:     mul     $[[T0]], $[[T0]], $6
-  ; MM32R3:     addu16  $[[T2]], $[[T2]], $[[T0]]
-  ; MM32R3:     addu16  $2, $[[T2]], $[[T3]]
+  ; MM32R3:     addu16  $2, $[[T2]], $[[T0]]
+  ; MM32R3:     mul     $[[T3:[0-9]+]], $4, $7
+  ; MM32R3:     addu16  $[[T2]], $[[T2]], $[[T3]]
 
-  ; MM32R6:     mul     $[[T0:[0-9]+]], $5, $7
-  ; MM32R6:     mul     $[[T1:[0-9]+]], $4, $7
-  ; MM32R6:     mul     $[[T2:[0-9]+]], $5, $6
-  ; MM32R6:     muhu    $[[T3:[0-9]+]], $5, $7
-  ; MM32R6:     addu16  $[[T2]], $[[T3]], $[[T2]]
-  ; MM32R6:     addu16  $2, $[[T2]], $[[T1]]
+  ; MM32R6:     mul     $[[T0:[0-9]+]], $5, $6
+  ; MM32R6:     muhu    $[[T1:[0-9]+]], $5, $7
+  ; MM32R6:     addu16  $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+  ; MM32R6:     mul     $[[T3:[0-9]+]], $4, $7
+  ; MM32R6:     addu16  $2, $[[T2]], $[[T3]]
+  ; MM32R6:     mul     $[[T1]], $5, $7
 
   %r = mul i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @mul_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: mul_i128:
 
   ; GP32:           lw      $25, %call16(__multi3)($gp)
 
   ; GP64-NOT-R6:    dmult   $4, $7
   ; GP64-NOT-R6:    mflo    $[[T0:[0-9]+]]
   ; GP64-NOT-R6:    dmult   $5, $6
   ; GP64-NOT-R6:    mflo    $[[T1:[0-9]+]]
   ; GP64-NOT-R6:    dmultu  $5, $7
   ; GP64-NOT-R6:    mflo    $3
   ; GP64-NOT-R6:    mfhi    $[[T2:[0-9]+]]
   ; GP64-NOT-R6:    daddu   $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; GP64-NOT-R6:    daddu   $2, $[[T3:[0-9]+]], $[[T0]]
 
-  ; 64R6-DAG:       dmul    $3, $5, $7
-  ; 64R6-DAG:       dmul    $[[T0:[0-9]+]], $4, $7
   ; 64R6-DAG:       dmul    $[[T1:[0-9]+]], $5, $6
   ; 64R6:           dmuhu   $[[T2:[0-9]+]], $5, $7
   ; 64R6:           daddu   $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; 64R6-DAG:       dmul    $[[T0:[0-9]+]], $4, $7
   ; 64R6:           daddu   $2, $[[T1]], $[[T0]]
+  ; 64R6-DAG:       dmul    $3, $5, $7
 
   ; MM32:           lw      $25, %call16(__multi3)($16)
 
   %r = mul i128 %a, %b
   ret i128 %r
 }

llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll

; ALL-LABEL: nor_i64:
   %r = xor i64 %or, -1
   ret i64 %r
 }
 
 define signext i128 @nor_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: nor_i128:
 
-  ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; GP32:         lw      $[[T1:[0-9]+]], 20($sp)
   ; GP32:         lw      $[[T2:[0-9]+]], 16($sp)
   ; GP32:         nor     $2, $[[T2]], $4
   ; GP32:         nor     $3, $[[T1]], $5
+  ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; GP32:         nor     $4, $[[T0]], $6
   ; GP32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; GP32:         nor     $5, $[[T3]], $7
 
   ; GP64:         nor     $2, $6, $4
   ; GP64:         nor     $3, $7, $5
 
-  ; MM32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; MM32:         lw      $[[T1:[0-9]+]], 20($sp)
   ; MM32:         lw      $[[T2:[0-9]+]], 16($sp)
   ; MM32:         nor     $2, $[[T2]], $4
   ; MM32:         nor     $3, $[[T1]], $5
+  ; MM32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; MM32:         nor     $4, $[[T0]], $6
   ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         nor     $5, $[[T3]], $7
 
   ; MM64:         nor     $2, $6, $4
   ; MM64:         nor     $3, $7, $5
 
   %or = or i128 %b, %a
   %r = xor i128 %or, -1
   ret i128 %r
 }

llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll

; ALL-LABEL: or_i64:
   %r = or i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @or_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: or_i128:
 
-  ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; GP32:         lw      $[[T1:[0-9]+]], 20($sp)
   ; GP32:         lw      $[[T2:[0-9]+]], 16($sp)
   ; GP32:         or      $2, $4, $[[T2]]
   ; GP32:         or      $3, $5, $[[T1]]
+  ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; GP32:         or      $4, $6, $[[T0]]
   ; GP32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; GP32:         or      $5, $7, $[[T3]]
 
   ; GP64:         or      $2, $4, $6
   ; GP64:         or      $3, $5, $7
 
-  ; MM32:         lw      $[[T0:[0-9]+]], 32($sp)
-  ; MM32:         lw      $[[T1:[0-9]+]], 28($sp)
-  ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 20($sp)
+  ; MM32:         lw      $[[T2:[0-9]+]], 16($sp)
   ; MM32:         or16    $[[T2]], $4
   ; MM32:         or16    $[[T1]], $5
+  ; MM32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; MM32:         or16    $[[T0]], $6
-  ; MM32:         lw      $[[T3:[0-9]+]], 36($sp)
+  ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         or16    $[[T3]], $7
 
   ; MM64:         or      $2, $4, $6
   ; MM64:         or      $3, $5, $7
 
   %r = or i128 %a, %b
   ret i128 %r
 }

llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll

entry:
   ; M2:         mtc1    $6, $f0
   ; M3:         mov.s   $f13, $f14
   ; M2-M3:      [[BB0]]:
   ; M2-M3:      jr      $ra
   ; M2:         mtc1    $5, $f0
   ; M3:         mov.s   $f0, $f13
 
   ; CMOV-32:    mtc1    $6, $f0
-  ; CMOV-32:    mtc1    $5, $f1
   ; CMOV-32:    andi    $[[T0:[0-9]+]], $4, 1
+  ; CMOV-32:    mtc1    $5, $f1
   ; CMOV-32:    movn.s  $f0, $f1, $[[T0]]
 
   ; SEL-32:     mtc1    $5, $[[F0:f[0-9]+]]
   ; SEL-32:     mtc1    $6, $[[F1:f[0-9]+]]
   ; SEL-32:     mtc1    $4, $f0
   ; SEL-32:     sel.s   $f0, $[[F1]], $[[F0]]
 
   ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV-64:    movn.s  $f14, $f13, $[[T0]]
   ; CMOV-64:    mov.s   $f0, $f14
 
   ; SEL-64:     mtc1    $4, $f0
   ; SEL-64:     sel.s   $f0, $f14, $f13
 
   ; MM32R3:     mtc1    $6, $[[F0:f[0-9]+]]
-  ; MM32R3:     mtc1    $5, $[[F1:f[0-9]+]]
   ; MM32R3:     andi16  $[[T0:[0-9]+]], $4, 1
+  ; MM32R3:     mtc1    $5, $[[F1:f[0-9]+]]
   ; MM32R3:     movn.s  $f0, $[[F1]], $[[T0]]
 
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
 define float @tst_select_i1_float_reordered(float %x, float %y,
                                             i1 signext %s) {

llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll

entry:
 
   ; CMOV-32:    andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV-32:    lw      $2, 16($sp)
   ; CMOV-32:    movn    $2, $6, $[[T0]]
   ; CMOV-32:    lw      $3, 20($sp)
   ; CMOV-32:    movn    $3, $7, $[[T0]]
 
   ; SEL-32:     andi    $[[T0:[0-9]+]], $4, 1
-  ; SEL-32:     selnez  $[[T1:[0-9]+]], $6, $[[T0]]
-  ; SEL-32:     lw      $[[T2:[0-9]+]], 16($sp)
-  ; SEL-32:     seleqz  $[[T3:[0-9]+]], $[[T2]], $[[T0]]
-  ; SEL-32:     or      $2, $[[T1]], $[[T3]]
-  ; SEL-32:     selnez  $[[T4:[0-9]+]], $7, $[[T0]]
-  ; SEL-32:     lw      $[[T5:[0-9]+]], 20($sp)
-  ; SEL-32:     seleqz  $[[T6:[0-9]+]], $[[T5]], $[[T0]]
-  ; SEL-32:     or      $3, $[[T4]], $[[T6]]
+  ; SEL-32:     lw      $[[T1:[0-9]+]], 16($sp)
+  ; SEL-32:     seleqz  $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+  ; SEL-32:     selnez  $[[T3:[0-9]+]], $6, $[[T0]]
+  ; SEL-32:     or      $2, $[[T3]], $[[T2]]
+  ; SEL-32:     lw      $[[T4:[0-9]+]], 20($sp)
+  ; SEL-32:     seleqz  $[[T5:[0-9]+]], $[[T4]], $[[T0]]
+  ; SEL-32:     selnez  $[[T6:[0-9]+]], $7, $[[T0]]
+  ; SEL-32:     or      $3, $[[T6]], $[[T5]]
 
   ; M3:         andi    $[[T0:[0-9]+]], $4, 1
   ; M3:         bnez    $[[T0]], [[BB0:\.LBB[0-9_]+]]
   ; M3:         nop
   ; M3:         move    $5, $6
   ; M3:         [[BB0]]:
   ; M3:         jr      $ra
   ; M3:         move    $2, $5
entry:
 
   ; MM32R3:     andi16  $[[T0:[0-9]+]], $4, 1
   ; MM32R3:     lw      $2, 16($sp)
   ; MM32R3:     movn    $2, $6, $[[T0]]
   ; MM32R3:     lw      $3, 20($sp)
   ; MM32R3:     movn    $3, $7, $[[T0]]
 
   ; MM32R6:     andi16  $[[T0:[0-9]+]], $4, 1
-  ; MM32R6:     selnez  $[[T1:[0-9]+]], $6, $[[T0]]
   ; MM32R6:     lw      $[[T2:[0-9]+]], 16($sp)
   ; MM32R6:     seleqz  $[[T3:[0-9]+]], $[[T2]], $[[T0]]
+  ; MM32R6:     selnez  $[[T1:[0-9]+]], $6, $[[T0]]
   ; MM32R6:     or      $2, $[[T1]], $[[T3]]
-  ; MM32R6:     selnez  $[[T6:[0-9]+]], $7, $[[T0]]
   ; MM32R6:     lw      $[[T4:[0-9]+]], 20($sp)
   ; MM32R6:     seleqz  $[[T5:[0-9]+]], $[[T4]], $[[T0]]
+  ; MM32R6:     selnez  $[[T6:[0-9]+]], $7, $[[T0]]
   ; MM32R6:     or      $3, $[[T6]], $[[T5]]
 
   %r = select i1 %s, i64 %x, i64 %y
   ret i64 %r
 }
 
 define i8* @tst_select_word_cst(i8* %a, i8* %b) {
   ; ALL-LABEL: tst_select_word_cst:

llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll

; ALL-LABEL: sub_i128:
   ; GP32-NOT-MM:    addu      $[[T11:[0-9]+]], $[[T10]], $[[T4]]
   ; GP32-NOT-MM:    subu      $4, $6, $[[T11]]
   ; GP32-NOT-MM:    move      $5, $[[T6]]
 
   ; GP32-MM:        lw        $[[T0:[0-9]+]], 20($sp)
   ; GP32-MM:        sltu      $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]]
   ; GP32-MM:        lw        $[[T3:[0-9]+]], 16($sp)
   ; GP32-MM:        addu      $[[T3]], $[[T1]], $[[T3]]
-  ; GP32-MM:        lw        $[[T5:[0-9]+]], 24($sp)
-  ; GP32-MM:        lw        $[[T4:[0-9]+]], 28($sp)
-  ; GP32-MM:        subu      $[[T1]], $7, $[[T4]]
-  ; GP32-MM:        subu      $[[T3]], $4, $[[T3]]
-  ; GP32-MM:        sltu      $[[T6:[0-9]+]], $6, $[[T5]]
+  ; GP32-MM:        lw        $[[T4:[0-9]+]], 24($sp)
+  ; GP32-MM:        lw        $[[T5:[0-9]+]], 28($sp)
+  ; GP32-MM:        subu      $[[T1]], $7, $[[T5]]
+  ; GP32-MM:        subu      $[[T3]], $[[T6:[0-9]+]], $[[T3]]
+  ; GP32-MM:        sltu      $[[T6]], $6, $[[T4]]
   ; GP32-MM:        addu      $[[T0]], $[[T6]], $[[T0]]
   ; GP32-MM:        subu      $[[T0]], $5, $[[T0]]
-  ; GP32-MM:        sltu      $[[T7:[0-9]+]], $7, $[[T4]]
-  ; GP32-MM:        addu      $[[T8:[0-8]+]], $[[T7]], $[[T5]]
-  ; GP32-MM:        subu      $[[T9:[0-9]+]], $6, $[[T8]]
+  ; GP32-MM:        sltu      $[[T6]], $7, $[[T5]]
+  ; GP32-MM:        addu      $[[T6]], $[[T6]], $[[T4]]
+  ; GP32-MM:        subu      $[[T6]], $6, $[[T6]]
   ; GP32-MM:        move      $[[T2]], $[[T1]]
 
   ; GP64:           dsubu     $3, $5, $7
   ; GP64:           sltu      $[[T0:[0-9]+]], $5, $7
   ; GP64:           daddu     $[[T1:[0-9]+]], $[[T0]], $6
   ; GP64:           dsubu     $2, $4, $[[T1]]
 
   %r = sub i128 %a, %b
   ret i128 %r
 }

llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll

; ALL-LABEL: xor_i64:
   %r = xor i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @xor_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: xor_i128:
 
-  ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; GP32:         lw      $[[T1:[0-9]+]], 20($sp)
   ; GP32:         lw      $[[T2:[0-9]+]], 16($sp)
   ; GP32:         xor     $2, $4, $[[T2]]
   ; GP32:         xor     $3, $5, $[[T1]]
+  ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; GP32:         xor     $4, $6, $[[T0]]
   ; GP32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; GP32:         xor     $5, $7, $[[T3]]
 
   ; GP64:         xor     $2, $4, $6
   ; GP64:         xor     $3, $5, $7
 
-  ; MM32:         lw      $[[T0:[0-9]+]], 32($sp)
-  ; MM32:         lw      $[[T1:[0-9]+]], 28($sp)
-  ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 20($sp)
+  ; MM32:         lw      $[[T2:[0-9]+]], 16($sp)
   ; MM32:         xor16   $[[T2]], $4
   ; MM32:         xor16   $[[T1]], $5
+  ; MM32:         lw      $[[T0:[0-9]+]], 24($sp)
   ; MM32:         xor16   $[[T0]], $6
-  ; MM32:         lw      $[[T3:[0-9]+]], 36($sp)
+  ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         xor16   $[[T3]], $7
 
   ; MM64:         xor     $2, $4, $6
   ; MM64:         xor     $3, $5, $7
 
   %r = xor i128 %a, %b
   ret i128 %r
 }

llvm/trunk/test/CodeGen/Mips/longbranch.ll

 ; N64-NEXT:  [[BB1]]:
 ; N64-NEXT:      daddu   $1, $ra, $1
 ; N64-NEXT:      ld      $ra, 0($sp)
 ; N64-NEXT:      jr      $1
 ; N64-NEXT:      daddiu  $sp, $sp, 16
 
 ; N64:   [[BB0]]:
 ; N64:        daddiu  $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1)))
-; N64:        ld      $[[R2:[0-9]+]], %got_disp(x)($[[GP]])
 ; N64:        addiu   $[[R3:[0-9]+]], $zero, 1
+; N64:        ld      $[[R2:[0-9]+]], %got_disp(x)($[[GP]])
 ; N64:        sw      $[[R3]], 0($[[R2]])
 ; N64:   [[BB2]]:
 ; N64:        jr      $ra
 ; N64:        nop
 
 ; In MIPS64R6 JR is an alias to JALR with $rd=0. As everything else remains the
 ; same with the N64 prefix, we use -asm-show-inst in order to make sure that
 ; the opcode of the MachineInst is a JALR.

llvm/trunk/test/CodeGen/Mips/no-odd-spreg.ll

 entry:
   ; Clobber all except $f12 and $f13
   ;
   ; The intention is that if odd single precision registers are permitted, the
   ; allocator will choose $f12 and $f13 to avoid the spill/reload.
   ;
   ; On the other hand, if odd single precision registers are not permitted, it
   ; will be forced to spill/reload either %a or %0.
+  ;
+  ; This is affected by scheduling as the new machine scheduler schedules the
+  ; two adds together, avoiding the spill+reload.
 
   %0 = fadd float %a, 1.0
   call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
   %1 = fadd float %a, %0
   ret float %1
 }
 
 ; ALL-LABEL:  two_floats:
-; ODDSPREG:       add.s $f13, $f12, ${{f[0-9]+}}
+; ODDSPREG:       add.s $f[[RES:[0-9]]], $f12, ${{f[0-9]+}}
+; ODDSPREG:       add.s ${{f[0-9]+}}, $f12, $f[[RES]]
 ; ODDSPREG-NOT:   swc1
 ; ODDSPREG-NOT:   lwc1
-; ODDSPREG:       add.s $f0, $f12, $f13
 
 ; NOODDSPREG:     add.s $[[T0:f[0-9]*[02468]]], $f12, ${{f[0-9]+}}
-; NOODDSPREG:     swc1 $[[T0]],
-; NOODDSPREG:     lwc1 $[[T1:f[0-9]*[02468]]],
-; NOODDSPREG:     add.s $f0, $f12, $[[T1]]
+; NOODDSPREG-NOT: swc1 $[[T0]],
+; NOODDSPREG-NOT: lwc1 $[[T1:f[0-9]*[02468]]],
+; NOODDSPREG:     add.s ${{f[0-9]+}}, $f12, $[[T0]]
 
 define double @two_doubles(double %a) {
 entry:
   ; Clobber all except $f12 and $f13
   ;
   ; -mno-odd-sp-reg doesn't need to affect double precision values so both cases
   ; use $f12 and $f13.
 
   %0 = fadd double %a, 1.0
   call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
   %1 = fadd double %a, %0
   ret double %1
 }
 
 ; ALL-LABEL: two_doubles:
-; ALL:           add.d $[[T0:f[0-9]+]], $f12, ${{f[0-9]+}}
-; ALL:           add.d $f0, $f12, $[[T0]]
+; ALL-DAG:        add.d $[[T0:f[0-9]+]], $f12, ${{f[0-9]+}}
+; ALL-DAG:        add.d $f0, $f12, $[[T0]]
 
 
 ; INVALID: -mattr=+nooddspreg is not currently permitted for a 32-bit FPU register file (FR=0 mode).

llvm/trunk/test/CodeGen/Mips/prevent-hoisting.ll

 ; RUN: llc -march=mipsel -O3 -relocation-model=pic < %s | FileCheck %s
 
 
 ; MIPS direct branches implicitly define register $at. This test makes sure that
 ; code hoisting optimization (which moves identical instructions at the start of
 ; two basic blocks to the common predecessor block) takes this into account and
 ; doesn't move definition of $at to the predecessor block (which would make $at
 ; live-in at the start of successor block).
 
 
 ; CHECK-LABEL: readLumaCoeff8x8_CABAC
 
 ; The check for first "addiu" instruction is added so that we can match the correct "b" instruction.
 ; CHECK:           andi
 ; CHECK:           b $[[BB0:BB[0-9_]+]]
-; CHECK-NEXT:      sll
+; CHECK:           sll
 
 ; Check that at the start of a fallthrough block there is a instruction that writes to $1.
-; CHECK-NEXT:  {{BB[0-9_#]+}}:
-; CHECK-NEXT:      lw      $[[R1:[0-9]+]], %got(assignSE2partition)($[[R2:[0-9]+]])
-; CHECK-NEXT:      sll $1, $[[R0:[0-9]+]], 4
+; CHECK:       {{BB[0-9_#]+}}:
+; CHECK:           sll $1, $[[R0:[0-9]+]], 4
+; CHECK:           lw      $[[R1:[0-9]+]], %got(assignSE2partition)($[[R2:[0-9]+]])
 
 ; Check that identical instructions are at the start of a target block.
 ; CHECK:       [[BB0]]:
-; CHECK-NEXT:      lw      $[[R1]], %got(assignSE2partition)($[[R2]])
-; CHECK-NEXT:      sll $1, $[[R0]], 4
+; CHECK:           sll $1, $[[R0]], 4
+; CHECK:           lw      $[[R1]], %got(assignSE2partition)($[[R2]])
 
 
 %struct.img_par = type { i32, i32, i32, i32, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [16 x [16 x i16]], [6 x [32 x i32]], [16 x [16 x i32]], [4 x [12 x [4 x [4 x i32]]]], [16 x i32], i8**, i32*, i32***, i32**, i32, i32, i32, i32, %struct.Slice*, %struct.macroblock*, i32, i32, i32, i32, i32, i32, %struct.DecRefPicMarking_s*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32***, i32***, i32****, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x [2 x i32]], [3 x [2 x i32]], i32, i32, i32, i32, %struct.timeb, %struct.timeb, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
 %struct.Slice = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.datapartition*, %struct.MotionInfoContexts*, %struct.TextureInfoContexts*, i32, i32*, i32*, i32*, i32, i32*, i32*, i32*, i32 (%struct.img_par*, %struct.inp_par*)*, i32, i32, i32, i32 }
 %struct.datapartition = type { %struct.Bitstream*, %struct.DecodingEnvironment, i32 (%struct.syntaxelement*, %struct.img_par*, %struct.datapartition*)* }
 %struct.Bitstream = type { i32, i32, i32, i32, i8*, i32 }
 %struct.DecodingEnvironment = type { i32, i32, i32, i32, i32, i8*, i32* }
 %struct.syntaxelement = type { i32, i32, i32, i32, i32, i32, i32, i32, void (i32, i32, i32*, i32*)*, void (%struct.syntaxelement*, %struct.img_par*, %struct.DecodingEnvironment*)* }

llvm/trunk/test/DebugInfo/Mips/dsr-fixed-objects.ll

 
 ; F0: DW_AT_name {{.*}}"e"
 ; F0: DW_TAG_variable
 ; F0-NEXT: DW_AT_location [DW_FORM_sec_offset]   ([[LOC:.*]])
 ; F0-NEXT: DW_AT_name [DW_FORM_strp]     ( .debug_str[0x0000006b] = "x")
 ;
 ; x -> DW_OP_reg1(51)
 ; F0: [[LOC]]: Beginning address offset: 0x0000000000000028
-; F0:             Ending address offset: 0x0000000000000030
+; F0:             Ending address offset: 0x000000000000002c
 ; F0:              Location description: 51
 
 define i32 @f0(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e) !dbg !4 {
 entry:
   %x = alloca i32, align 4
   tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !9,  metadata !DIExpression()), !dbg !27
   tail call void @llvm.dbg.value(metadata i32 %b, i64 0, metadata !10, metadata !DIExpression()), !dbg !28
   tail call void @llvm.dbg.value(metadata i32 %c, i64 0, metadata !11, metadata !DIExpression()), !dbg !29

 ; F1: DW_AT_name {{.*}}"x"
 ; F1: DW_AT_name {{.*}}"e"
 ; F1: DW_TAG_variable
 ; F1-NEXT: DW_AT_location [DW_FORM_sec_offset]   ([[LOC:.*]])
 ; F1-NEXT: DW_AT_name [DW_FORM_strp]     ( .debug_str[0x0000006b] = "x")
 
 ; x -> DW_OP_reg1(51)
 ; F1: [[LOC]]: Beginning address offset: 0x0000000000000080
-; F1:             Ending address offset: 0x0000000000000088
+; F1:             Ending address offset: 0x0000000000000084
 ; F1:              Location description: 51
 
 define i32 @f1(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e) !dbg !15 {
 entry:
   %x = alloca i32, align 16
   tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !17, metadata !DIExpression()), !dbg !46
   tail call void @llvm.dbg.value(metadata i32 %b, i64 0, metadata !18, metadata !DIExpression()), !dbg !47
   tail call void @llvm.dbg.value(metadata i32 %c, i64 0, metadata !19, metadata !DIExpression()), !dbg !48