AMDGPU: Don't fold subregister extracts into tied operands

[arsenm]

Summary

Should fix problem found with D22556

[• tstellarAMD]

LGTM.

[arsenm]

r278676

lib/Target/AMDGPU/SIFoldOperands.cpp

static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI,
                         unsigned UseOpIdx,
                         std::vector<FoldCandidate> &FoldList,
                         SmallVectorImpl<MachineInstr *> &CopiesToReplace,
                         const SIInstrInfo *TII, const SIRegisterInfo &TRI,
                         MachineRegisterInfo &MRI) {
   const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx);
 
   // FIXME: Fold operands with subregs.
-  if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) ||
-      UseOp.isImplicit())) {
+  if (UseOp.isReg() && OpToFold.isReg()) {
+    if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister)
+      return;
+
+    // Don't fold subregister extracts into tied operands, only if it is a full
+    // copy since a subregister use tied to a full register def doesn't really
+    // make sense. e.g. don't fold:
+    //
+    // %vreg1 = COPY %vreg0:sub1
+    // %vreg2<tied3> = V_MAC_F32 %vreg3, %vreg4, %vreg1<tied0>
+    //
+    //  into
+    // %vreg2<tied3> = V_MAC_F32 %vreg3, %vreg4, %vreg0:sub1<tied0>
+    if (UseOp.isTied() && OpToFold.getSubReg() != AMDGPU::NoSubRegister)
       return;
   }
 
   bool FoldingImm = OpToFold.isImm();
   APInt Imm;
 
   if (FoldingImm) {
     unsigned UseReg = UseOp.getReg();
     const TargetRegisterClass *UseRC

test/CodeGen/AMDGPU/operand-folding.ll

entry:
   %vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 1
   %vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 2
   %vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
   %tmp4 = xor <4 x i32> <i32 100, i32 100, i32 100, i32 100>, %vec3
   store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %out
   ret void
 }
 
+; A subregister use operand should not be tied.
+; CHECK-LABEL: {{^}}no_fold_tied_subregister:
+; CHECK: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
+; CHECK: v_mac_f32_e32 v[[LO]], 0x41200000, v[[HI]]
+; CHECK: buffer_store_dword v[[LO]]
+define void @no_fold_tied_subregister() {
+  %tmp1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef
+  %tmp2 = extractelement <2 x float> %tmp1, i32 0
+  %tmp3 = extractelement <2 x float> %tmp1, i32 1
+  %tmp4 = fmul float %tmp3, 10.0
+  %tmp5 = fadd float %tmp4, %tmp2
+  store volatile float %tmp5, float addrspace(1)* undef
+  ret void
+}
+
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
 attributes #0 = { nounwind readnone }