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Differential D23401

AMDGPU/SI: Fix a test in wqm.ll to always use s_cbranch_vcc*
ClosedPublic

Authored by • tstellarAMD on Aug 11 2016, 4:18 AM.

Details

Reviewers
nhaehnle
arsenm
Commits
rGa1619cd9aa0c: AMDGPU/SI: Fix a test in wqm.ll to always use s_cbranch_vcc*
rL279148: AMDGPU/SI: Fix a test in wqm.ll to always use s_cbranch_vcc*
Summary

We need to use floating-point compares to ensure that s_cbranch_vcc*
instructions are always generated. With integer compares, future
optimizations could cause s_cbranch_scc* to be generated instead.

Diff Detail

Repository
rL LLVM

Event Timeline

• tstellarAMD updated this revision to Diff 67674.Aug 11 2016, 4:18 AM
• tstellarAMD retitled this revision from to AMDGPU/SI: Fix a test in wqm.ll to always use s_cbranch_vcc*.
• tstellarAMD updated this object.
• tstellarAMD added reviewers: nhaehnle, arsenm.
• tstellarAMD added a subscriber: llvm-commits.
Herald added a subscriber: kzhuravl. · View Herald TranscriptAug 11 2016, 4:18 AM
nhaehnle accepted this revision.Aug 11 2016, 5:12 AM
nhaehnle edited edge metadata.

LGTM

This revision is now accepted and ready to land.Aug 11 2016, 5:12 AM
Closed by commit rL279148: AMDGPU/SI: Fix a test in wqm.ll to always use s_cbranch_vcc* (authored by tstellar). · Explain WhyAug 18 2016, 2:29 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
test/
CodeGen/
AMDGPU/
14 lines

Diff 68607

llvm/trunk/test/CodeGen/AMDGPU/wqm.ll

Show First 20 Lines • Show All 337 Lines • ▼ Show 20 Lines
; CHECK-LABEL: {{^}}test_loop_vcc: ; CHECK-LABEL: {{^}}test_loop_vcc:
; CHECK-NEXT: ; %entry ; CHECK-NEXT: ; %entry
; CHECK-NEXT: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec ; CHECK-NEXT: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
; CHECK: s_wqm_b64 exec, exec ; CHECK: s_wqm_b64 exec, exec
; CHECK: s_and_b64 exec, exec, [[LIVE]] ; CHECK: s_and_b64 exec, exec, [[LIVE]]
; CHECK: image_store ; CHECK: image_store
; CHECK: s_wqm_b64 exec, exec ; CHECK: s_wqm_b64 exec, exec
; CHECK: v_mov_b32_e32 [[CTR:v[0-9]+]], 0 ; CHECK-DAG: v_mov_b32_e32 [[CTR:v[0-9]+]], 0
; CHECK-DAG: v_mov_b32_e32 [[SEVEN:v[0-9]+]], 0x40e00000
; CHECK: s_branch [[LOOPHDR:BB[0-9]+_[0-9]+]] ; CHECK: s_branch [[LOOPHDR:BB[0-9]+_[0-9]+]]
; CHECK: v_add_i32_e32 [[CTR]], vcc, 2, [[CTR]] ; CHECK: v_add_f32_e32 [[CTR]], 2.0, [[CTR]]
; CHECK: [[LOOPHDR]]: ; %loop ; CHECK: [[LOOPHDR]]: ; %loop
; CHECK: v_cmp_lt_i32_e32 vcc, 7, [[CTR]] ; CHECK: v_cmp_lt_f32_e32 vcc, [[SEVEN]], [[CTR]]
; CHECK: s_cbranch_vccz ; CHECK: s_cbranch_vccz
; CHECK: ; %break ; CHECK: ; %break
; CHECK: ; return ; CHECK: ; return
define amdgpu_ps <4 x float> @test_loop_vcc(<4 x float> %in) nounwind { define amdgpu_ps <4 x float> @test_loop_vcc(<4 x float> %in) nounwind {
entry: entry:
call void @llvm.amdgcn.image.store.v4i32(<4 x float> %in, <4 x i32> undef, <8 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0) call void @llvm.amdgcn.image.store.v4i32(<4 x float> %in, <4 x i32> undef, <8 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0)
br label %loop br label %loop
loop: loop:
%ctr.iv = phi i32 [ 0, %entry ], [ %ctr.next, %body ] %ctr.iv = phi float [ 0.0, %entry ], [ %ctr.next, %body ]
%c.iv = phi <4 x float> [ %in, %entry ], [ %c.next, %body ] %c.iv = phi <4 x float> [ %in, %entry ], [ %c.next, %body ]
%cc = icmp sgt i32 %ctr.iv, 7 %cc = fcmp ogt float %ctr.iv, 7.0
br i1 %cc, label %break, label %body br i1 %cc, label %break, label %body
body: body:
%c.i = bitcast <4 x float> %c.iv to <4 x i32> %c.i = bitcast <4 x float> %c.iv to <4 x i32>
%c.next = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c.i, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %c.next = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c.i, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%ctr.next = add i32 %ctr.iv, 2 %ctr.next = fadd float %ctr.iv, 2.0
br label %loop br label %loop
break: break:
ret <4 x float> %c.iv ret <4 x float> %c.iv
} }
; Only intrinsic stores need exact execution -- other stores do not have ; Only intrinsic stores need exact execution -- other stores do not have
; externally visible effects and may require WQM for correctness. ; externally visible effects and may require WQM for correctness.
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