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Differential D23374

Fix typo in lowering for fp128 ueq
ClosedPublic

Authored by efriedma on Aug 10 2016, 1:59 PM.

Details

Reviewers
t.p.northover
petarj
hfinkel
Commits
rG98151d6440a0: Fix typo in lowering for fp128 ueq.
rL278750: Fix typo in lowering for fp128 ueq.
Summary

Regression from r259791.

Diff Detail

Repository
rL LLVM

Event Timeline

efriedma updated this revision to Diff 67598.Aug 10 2016, 1:59 PM
efriedma retitled this revision from to Fix typo in lowering for fp128 ueq.
efriedma updated this object.
efriedma added reviewers: t.p.northover, hfinkel, petarj.
efriedma set the repository for this revision to rL LLVM.
efriedma added a subscriber: llvm-commits.
petarj edited edge metadata.Aug 12 2016, 3:54 PM

lgtm

Closed by commit rL278750: Fix typo in lowering for fp128 ueq. (authored by efriedma). · Explain WhyAug 15 2016, 2:54 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
SelectionDAG/
2 lines
test/
CodeGen/
AArch64/
22 lines

Diff 68084

llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Show First 20 Lines • Show All 210 Lines • ▼ Show 20 Lines LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
(VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
(VT == MVT::f64) ? RTLIB::OGT_F64 : (VT == MVT::f64) ? RTLIB::OGT_F64 :
(VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
break; break;
case ISD::SETUEQ: case ISD::SETUEQ:
LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
(VT == MVT::f64) ? RTLIB::UO_F64 : (VT == MVT::f64) ? RTLIB::UO_F64 :
(VT == MVT::f128) ? RTLIB::UO_F64 : RTLIB::UO_PPCF128; (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
(VT == MVT::f64) ? RTLIB::OEQ_F64 : (VT == MVT::f64) ? RTLIB::OEQ_F64 :
(VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
break; break;
default: default:
// Invert CC for unordered comparisons // Invert CC for unordered comparisons
ShouldInvertCC = true; ShouldInvertCC = true;
switch (CCCode) { switch (CCCode) {
▲ Show 20 Lines • Show All 3,337 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/arm64-fp128.ll

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
; CHECK: bl __letf2 ; CHECK: bl __letf2
; CHECK: cmp w0, #0 ; CHECK: cmp w0, #0
; CHECK: cset w0, gt ; CHECK: cset w0, gt
ret i1 %val ret i1 %val
; CHECK: ret ; CHECK: ret
} }
define i1 @test_setcc3() {
; CHECK-LABEL: test_setcc3:
%lhs = load fp128, fp128* @lhs, align 16
%rhs = load fp128, fp128* @rhs, align 16
; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
%val = fcmp ueq fp128 %lhs, %rhs
; CHECK: bl __eqtf2
; CHECK: cmp w0, #0
; CHECK: cset w19, eq
; CHECK: bl __unordtf2
; CHECK: cmp w0, #0
; CHECK: cset w8, ne
; CHECK: orr w0, w8, w19
ret i1 %val
; CHECK: ret
}
define i32 @test_br_cc() { define i32 @test_br_cc() {
; CHECK-LABEL: test_br_cc: ; CHECK-LABEL: test_br_cc:
%lhs = load fp128, fp128* @lhs, align 16 %lhs = load fp128, fp128* @lhs, align 16
%rhs = load fp128, fp128* @rhs, align 16 %rhs = load fp128, fp128* @rhs, align 16
; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs] ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs] ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines