[SystemZ] Add some missing instruction classes and instructions

[• zhanjunl]

Summary

Add instruction formats E, RSI, SSd, SSE, and SSF.

Added BRXH, BRXLE, PR, MVCK, STRAG, and ECTG instructions to test out
those formats.

[uweigand]

Looks basically good to me. Some of the instructions don't have the appropriate flags set -- see inline comments. This is important even for instructions not used for codegen, since those flags can be queried via the disassembler interface (e.g. LLDB uses this to detect branches). Patch OK with those changes.

lib/Target/SystemZ/SystemZInstrInfo.td

341

These should have the isBranch and isTerminator flags set. Maybe we should have a BranchBinaryRSI helper similar to BranchUnaryRI ...

1687

PR actually changes a lot of registers and has other side effects. It probably doesn't matter too much since this instruction isn't usable on Linux anyway, but at least we should have the hasSideEffects flag.

1691

Should have the mayLoad and mayStore flags.

1695

Should have the mayStore flag.

1700

Should have the mayLoad flag.

[• zhanjunl]

Thanks for the review Ulrich, I'll try to remember to set the right flags next time.

[• zhanjunl]

Uploaded wrong diff...

[uweigand]

LGTM, thanks.

[• zhanjunl]

Added a comment to describe BranchBinary.

lib/Target/SystemZ/SystemZInstrFormats.td

 //   bits<4> Mn   : mode value for operand n
 //
 // The operand numbers ("n" in the list above) follow the architecture manual.
 // Assembly operands sometimes have a different order; in particular, R3 often
 // is often written between operands 1 and 2.
 //
 //===----------------------------------------------------------------------===//
 
+class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSystemZ<2, outs, ins, asmstr, pattern> {
+  field bits<16> Inst;
+  field bits<16> SoftFail = 0;
+
+  let Inst = op;
+}
+
 class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<2, outs, ins, asmstr, pattern> {
   field bits<16> Inst;
   field bits<16> SoftFail = 0;
 
   bits<8> I1;
 
   let Inst{15-8} = op;
class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   bits<16> BD2;
 
   let Inst{31-24} = op;
   let Inst{23-20} = R1;
   let Inst{19-16} = R3;
   let Inst{15-0}  = BD2;
 }
 
+class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSystemZ<4, outs, ins, asmstr, pattern> {
+  field bits<32> Inst;
+  field bits<32> SoftFail = 0;
+
+  bits<4> R1;
+  bits<4> R3;
+  bits<16> RI2;
+
+  let Inst{31-24} = op;
+  let Inst{23-20} = R1;
+  let Inst{19-16} = R3;
+  let Inst{15-0}  = RI2;
+}
+
 class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
   field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R3;
   bits<24> BD2;
class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   bits<24> BDL1;
   bits<16> BD2;
 
   let Inst{47-40} = op;
   let Inst{39-16} = BDL1;
   let Inst{15-0}  = BD2;
 }
 
+class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSystemZ<6, outs, ins, asmstr, pattern> {
+  field bits<48> Inst;
+  field bits<48> SoftFail = 0;
+
+  bits<20> XBD1;
+  bits<16> BD2;
+  bits<4> R3;
+
+  let Inst{47-40} = op;
+  let Inst{39-36} = XBD1{19-16};
+  let Inst{35-32} = R3;
+  let Inst{31-16} = XBD1{15-0};
+  let Inst{15-0}  = BD2;
+}
+
+class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSystemZ<6, outs, ins, asmstr, pattern> {
+  field bits<48> Inst;
+  field bits<48> SoftFail = 0;
+
+  bits<16> BD1;
+  bits<16> BD2;
+
+  let Inst{47-32} = op;
+  let Inst{31-16} = BD1;
+  let Inst{15-0}  = BD2;
+}
+
+class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSystemZ<6, outs, ins, asmstr, pattern> {
+  field bits<48> Inst;
+  field bits<48> SoftFail = 0;
+
+  bits<16> BD1;
+  bits<16> BD2;
+  bits<4>  R3;
+
+  let Inst{47-40} = op{11-4};
+  let Inst{39-36} = R3;
+  let Inst{35-32} = op{3-0};
+  let Inst{31-16} = BD1;
+  let Inst{15-0}  = BD2;
+}
+
 class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
   field bits<32> SoftFail = 0;
 
   bits<16> BD2;
 
   let Inst{31-16} = op;
class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
   : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2),
            mnemonic##"\t$R1, $I2", []> {
   let isBranch = 1;
   let isTerminator = 1;
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
 }
 
+class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
+  : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
+            mnemonic##"\t$R1, $R3, $RI2", []> {
+  let isBranch = 1;
+  let isTerminator = 1;
+  let Constraints = "$R1 = $R1src";
+  let DisableEncoding = "$R1src";
+}
+
 class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
                      AddressingMode mode = bdaddr12only>
   : InstRS<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
            mnemonic#"\t$R1, $R3, $BD2", []> {
   let mayLoad = 1;
 }
 
 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,

lib/Target/SystemZ/SystemZInstrInfo.td

 
 // Decrement a register and branch if it is nonzero.  These don't clobber CC,
 // but we might need to split long branches into sequences that do.
 let Defs = [CC] in {
   def BRCT  : BranchUnaryRI<"brct",  0xA76, GR32>;
   def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;
 }
 
+def BRXH : BranchBinaryRSI<"brxh", 0x84, GR64>;
+def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR64>;
+
 //===----------------------------------------------------------------------===//
 // Select instructions
 //===----------------------------------------------------------------------===//
 
 def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>;
 def Select32    : SelectWrapper<GR32>;
 def Select64    : SelectWrapper<GR64>;
 
 // We don't define 32-bit Mux stores because the low-only STOC should

 
 let hasSideEffects = 1 in {
   def EX   : InstRX<0x44, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
                   "ex\t$R1, $XBD2", []>;
   def EXRL : InstRIL<0xC60, (outs), (ins GR64:$R1, pcrel32:$I2),
                      "exrl\t$R1, $I2", []>;
 }
 
+let Defs = [CC] in {
+  let hasSideEffects = 1 in
+    def PR : InstE<0x0101, (outs), (ins), "pr", []>;
+
+  let mayLoad = 1, mayStore = 1 in
+    def MVCK : InstSSd<0xD9, (outs),
+                             (ins bdxaddr12only:$XBD1, bdaddr12only:$BD2,
+                                  GR64:$R3),
+                       "mvck\t$XBD1, $BD2, $R3", []>;
+}
+
+let mayStore = 1 in
+  def STRAG : InstSSE<0xE502, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
+                      "strag\t$BD1, $BD2", []>;
+
+let Defs = [R0D, R1D], mayLoad = 1 in
+  def ECTG : InstSSF<0xC81, (outs),
+                            (ins bdaddr12only:$BD1, bdaddr12only:$BD2, GR64:$R3),
+                     "ectg\t$BD1, $BD2, $R3", []>;
 
 //===----------------------------------------------------------------------===//
 // Peepholes.
 //===----------------------------------------------------------------------===//
 
 // Use AL* for GR64 additions of unsigned 32-bit values.
 defm : ZXB<add, GR64, ALGFR>;
 def  : Pat<(add GR64:$src1, imm64zx32:$src2),

test/MC/Disassembler/SystemZ/insns-pcrel.txt

 
 # 0x000009fc:
 # CHECK: exrl %r0, 0x1000009fa
 0xc6 0x00 0x7f 0xff 0xff 0xff
 
 # 0x00000a02:
 # CHECK: exrl %r15, 0x100000a00
 0xc6 0xf0 0x7f 0xff 0xff 0xff
+
+# 0x00000a08:
+# CHECK: brxh %r0, %r1, 0xa08
+0x84 0x01 0x00 0x00
+
+# 0x00000a0c:
+# CHECK: brxh %r14, %r1, 0xa0c
+0x84 0xe1 0x00 0x00
+
+# 0x00000a10:
+# CHECK: brxh %r15, %r1, 0xa10
+0x84 0xf1 0x00 0x00
+
+# 0x00000a14:
+# CHECK: brxh %r0, %r1, 0xa12
+0x84 0x01 0xff 0xff
+
+# 0x00000a18:
+# CHECK: brxh %r14, %r1, 0xffffffffffff0a18
+0x84 0xe1 0x80 0x00
+
+# 0x00000a1c:
+# CHECK: brxh %r15, %r1, 0x10a1a
+0x84 0xf1 0x7f 0xff
+
+# 0x00000a20:
+# CHECK: brxle %r0, %r1, 0xa20
+0x85 0x01 0x00 0x00
+
+# 0x00000a24:
+# CHECK: brxle %r14, %r1, 0xa24
+0x85 0xe1 0x00 0x00
+
+# 0x00000a28:
+# CHECK: brxle %r15, %r1, 0xa28
+0x85 0xf1 0x00 0x00
+
+# 0x00000a2c:
+# CHECK: brxle %r0, %r1, 0xa2a
+0x85 0x01 0xff 0xff
+
+# 0x00000a30:
+# CHECK: brxle %r14, %r1, 0xffffffffffff0a30
+0x85 0xe1 0x80 0x00
+
+# 0x00000a34:
+# CHECK: brxle %r15, %r1, 0x10a32
+0x85 0xf1 0x7f 0xff

test/MC/Disassembler/SystemZ/insns.txt

 0xb2 0x4f 0x00 0xf0
 
 # CHECK: ear %r7, %a8
 0xb2 0x4f 0x00 0x78
 
 # CHECK: ear %r15, %a15
 0xb2 0x4f 0x00 0xff
 
+# CHECK: ectg 0, 0, %r0
+0xc8 0x01 0x00 0x00 0x00 0x00
+
+# CHECK: ectg 0, 4095, %r2
+0xc8 0x21 0x00 0x00 0x0f 0xff
+
+# CHECK: ectg 0, 0(%r1), %r2
+0xc8 0x21 0x00 0x00 0x10 0x00
+
+# CHECK: ectg 0, 0(%r15), %r2
+0xc8 0x21 0x00 0x00 0xf0 0x00
+
+# CHECK: ectg 0(%r1), 4095(%r15), %r2
+0xc8 0x21 0x10 0x00 0xff 0xff
+
+# CHECK: ectg 0(%r1), 0(%r15), %r2
+0xc8 0x21 0x10 0x00 0xf0 0x00
+
+# CHECK: ectg 4095(%r1), 0(%r15), %r2
+0xc8 0x21 0x1f 0xff 0xf0 0x00
+
 # CHECK: etnd %r0
 0xb2 0xec 0x00 0x00
 
 # CHECK: etnd %r15
 0xb2 0xec 0x00 0xf0
 
 # CHECK: etnd %r7
 0xb2 0xec 0x00 0x70

 0xd2 0x00 0xff 0xff 0x00 0x00
 
 # CHECK: mvc 0(256,%r1), 0
 0xd2 0xff 0x10 0x00 0x00 0x00
 
 # CHECK: mvc 0(256,%r15), 0
 0xd2 0xff 0xf0 0x00 0x00 0x00
 
+# CHECK: mvck 0, 0, %r0
+0xd9 0x00 0x00 0x00 0x00 0x00
+
+# CHECK: mvck 0, 4095, %r2
+0xd9 0x02 0x00 0x00 0x0f 0xff
+
+# CHECK: mvck 0, 0(%r1), %r2
+0xd9 0x02 0x00 0x00 0x10 0x00
+
+# CHECK: mvck 0, 0(%r15), %r2
+0xd9 0x02 0x00 0x00 0xf0 0x00
+
+# CHECK: mvck 0(%r1), 4095(%r15), %r2
+0xd9 0x02 0x10 0x00 0xff 0xff
+
+# CHECK: mvck 0(%r1), 0(%r15), %r2
+0xd9 0x02 0x10 0x00 0xf0 0x00
+
+# CHECK: mvck 4095(%r15,%r1), 0(%r15), %r2
+0xd9 0xf2 0x1f 0xff 0xf0 0x00
+
 # CHECK: mvghi 0, 0
 0xe5 0x48 0x00 0x00 0x00 0x00
 
 # CHECK: mvghi 4095, 0
 0xe5 0x48 0x0f 0xff 0x00 0x00
 
 # CHECK: mvghi 0, -32768
 0xe5 0x48 0x00 0x00 0x80 0x00

 0xe3 0x01 0xff 0xff 0x7f 0x36
 
 # CHECK: pfd 0, 524287(%r15,%r1)
 0xe3 0x0f 0x1f 0xff 0x7f 0x36
 
 # CHECK: pfd 15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x36
 
+# CHECK: pr
+0x01 0x01
+
 # CHECK: popcnt %r0, %r0
 0xb9 0xe1 0x00 0x00
 
 # CHECK: popcnt %r0, %r15
 0xb9 0xe1 0x00 0x0f
 
 # CHECK: popcnt %r15, %r0
 0xb9 0xe1 0x00 0xf0

 0xeb 0x00 0xf0 0x00 0x00 0x90
 
 # CHECK: stmy %r0, %r0, 524287(%r1)
 0xeb 0x00 0x1f 0xff 0x7f 0x90
 
 # CHECK: stmy %r0, %r0, 524287(%r15)
 0xeb 0x00 0xff 0xff 0x7f 0x90
 
+# CHECK: strag 0, 0
+0xe5 0x02 0x00 0x00 0x00 0x00
+
+# CHECK: strag 0, 4095
+0xe5 0x02 0x00 0x00 0x0f 0xff
+
+# CHECK: strag 0, 0(%r1)
+0xe5 0x02 0x00 0x00 0x10 0x00
+
+# CHECK: strag 0, 0(%r15)
+0xe5 0x02 0x00 0x00 0xf0 0x00
+
+# CHECK: strag 0(%r1), 4095(%r15)
+0xe5 0x02 0x10 0x00 0xff 0xff
+
+# CHECK: strag 4095(%r1), 0(%r15)
+0xe5 0x02 0x1f 0xff 0xf0 0x00
+
 # CHECK: strvg %r0, -524288
 0xe3 0x00 0x00 0x00 0x80 0x2f
 
 # CHECK: strvg %r0, -1
 0xe3 0x00 0x0f 0xff 0xff 0x2f
 
 # CHECK: strvg %r0, 0
 0xe3 0x00 0x00 0x00 0x00 0x2f

test/MC/SystemZ/insn-bad.s

 #CHECK: error: offset out of range
 #CHECK: brctg %r0, 0x10000
 
   brctg %r0, -0x100002
   brctg %r0, -1
   brctg %r0, 1
   brctg %r0, 0x10000
 
+#CHECK: error: offset out of range
+#CHECK: brxh  %r0, %r2, -0x100002
+#CHECK: error: offset out of range
+#CHECK: brxh  %r0, %r2, -1
+#CHECK: error: offset out of range
+#CHECK: brxh  %r0, %r2, 1
+#CHECK: error: offset out of range
+#CHECK: brxh  %r0, %r2, 0x10000
+
+  brxh  %r0, %r2, -0x100002
+  brxh  %r0, %r2, -1
+  brxh  %r0, %r2, 1
+  brxh  %r0, %r2, 0x10000
+
+#CHECK: error: offset out of range
+#CHECK: brxle %r0, %r2, -0x100002
+#CHECK: error: offset out of range
+#CHECK: brxle %r0, %r2, -1
+#CHECK: error: offset out of range
+#CHECK: brxle %r0, %r2, 1
+#CHECK: error: offset out of range
+#CHECK: brxle %r0, %r2, 0x10000
+
+  brxle %r0, %r2, -0x100002
+  brxle %r0, %r2, -1
+  brxle %r0, %r2, 1
+  brxle %r0, %r2, 0x10000
+
 #CHECK: error: invalid operand
 #CHECK: c %r0, -1
 #CHECK: error: invalid operand
 #CHECK: c %r0, 4096
 
   c %r0, -1
   c %r0, 4096
 

 #CHECK: error: invalid operand
 #CHECK: ex      %r0, -1
 #CHECK: error: invalid operand
 #CHECK: ex      %r0, 4096
 
         ex      %r0, -1
         ex      %r0, 4096
 
+#CHECK: error: invalid use of indexed addressing
+#CHECK: ectg    160(%r1,%r15),160(%r15), %r2
+#CHECK: error: invalid operand
+#CHECK: ectg    -1(%r1),160(%r15), %r2
+#CHECK: error: invalid operand
+#CHECK: ectg    4096(%r1),160(%r15), %r2
+#CHECK: error: invalid operand
+#CHECK: ectg    0(%r1),-1(%r15), %r2
+#CHECK: error: invalid operand
+#CHECK: ectg    0(%r1),4096(%r15), %r2
+
+        ectg    160(%r1,%r15),160(%r15), %r2
+        ectg    -1(%r1),160(%r15), %r2
+        ectg    4096(%r1),160(%r15), %r2
+        ectg    0(%r1),-1(%r15), %r2
+        ectg    0(%r1),4096(%r15), %r2
+
 #CHECK: error: invalid operand
 #CHECK: fidbr %f0, -1, %f0
 #CHECK: error: invalid operand
 #CHECK: fidbr %f0, 16, %f0
 
   fidbr %f0, -1, %f0
   fidbr %f0, 16, %f0
 
#CHECK: mvc 0(-), 0
   mvc  0(1,%r1), -1(%r1)
   mvc  0(1,%r1), 4096(%r1)
   mvc  0(1,%r0), 0(%r1)
   mvc  0(1,%r1), 0(%r0)
   mvc  0(%r1,%r2), 0(%r1)
   mvc  0(1,%r2), 0(%r1,%r2)
   mvc 0(-), 0
 
+#CHECK: error: invalid use of length addressing
+#CHECK: mvck  0(%r1,%r1), 0(2,%r1), %r3
+#CHECK: error: %r0 used in an address
+#CHECK: mvck  0(%r0,%r1), 0(%r1), %r3
+#CHECK: error: invalid operand
+#CHECK: mvck  -1(%r1,%r1), 0(%r1), %r3
+#CHECK: error: invalid operand
+#CHECK: mvck  4096(%r1,%r1), 0(%r1), %r3
+#CHECK: error: invalid operand
+#CHECK: mvck  0(%r1,%r1), -1(%r1), %r3
+#CHECK: error: invalid operand
+#CHECK: mvck  0(%r1,%r1), 4096(%r1), %r3
+#CHECK: error: %r0 used in an address
+#CHECK: mvck  0(%r1,%r0), 0(%r1), %r3
+#CHECK: error: %r0 used in an address
+#CHECK: mvck  0(%r1,%r1), 0(%r0), %r3
+#CHECK: error: invalid use of indexed addressing
+#CHECK: mvck  0(%r1,%r2), 0(%r1,%r2), %r3
+#CHECK: error: unknown token in expression
+#CHECK: mvck  0(-), 0, %r3
+
+  mvck  0(%r1,%r1), 0(2,%r1), %r3
+  mvck  0(%r0,%r1), 0(%r1), %r3
+  mvck  -1(%r1,%r1), 0(%r1), %r3
+  mvck  4096(%r1,%r1), 0(%r1), %r3
+  mvck  0(%r1,%r1), -1(%r1), %r3
+  mvck  0(%r1,%r1), 4096(%r1), %r3
+  mvck  0(%r1,%r0), 0(%r1), %r3
+  mvck  0(%r1,%r1), 0(%r0), %r3
+  mvck  0(%r1,%r2), 0(%r1,%r2), %r3
+  mvck  0(-), 0, %r3
+
 #CHECK: error: invalid operand
 #CHECK: mvghi -1, 0
 #CHECK: error: invalid operand
 #CHECK: mvghi 4096, 0
 #CHECK: error: invalid use of indexed addressing
 #CHECK: mvghi 0(%r1,%r2), 0
 #CHECK: error: invalid operand
 #CHECK: mvghi 0, -32769
#CHECK: pfdrl 1, 0x100000000
   pfdrl 1, 0x100000000
 
 #CHECK: error: {{(instruction requires: population-count)?}}
 #CHECK: popcnt  %r0, %r0
 
   popcnt  %r0, %r0
 
 #CHECK: error: invalid operand
+#CHECK: pr    %r0
+        pr    %r0
+
+#CHECK: error: invalid operand
 #CHECK: risbg %r0,%r0,0,0,-1
 #CHECK: error: invalid operand
 #CHECK: risbg %r0,%r0,0,0,64
 #CHECK: error: invalid operand
 #CHECK: risbg %r0,%r0,0,-1,0
 #CHECK: error: invalid operand
 #CHECK: risbg %r0,%r0,0,256,0
 #CHECK: error: invalid operand

 #CHECK: stmy  %r0, %r0, 524288
 #CHECK: error: invalid use of indexed addressing
 #CHECK: stmy  %r0, %r0, 0(%r1,%r2)
 
   stmy  %r0, %r0, -524289
   stmy  %r0, %r0, 524288
   stmy  %r0, %r0, 0(%r1,%r2)
 
+#CHECK: error: invalid use of indexed addressing
+#CHECK: strag   160(%r1,%r15),160(%r15)
+#CHECK: error: invalid operand
+#CHECK: strag   -1(%r1),160(%r15)
+#CHECK: error: invalid operand
+#CHECK: strag   4096(%r1),160(%r15)
+#CHECK: error: invalid operand
+#CHECK: strag   0(%r1),-1(%r15)
+#CHECK: error: invalid operand
+#CHECK: strag   0(%r1),4096(%r15)
+
+        strag   160(%r1,%r15),160(%r15)
+        strag   -1(%r1),160(%r15)
+        strag   4096(%r1),160(%r15)
+        strag   0(%r1),-1(%r15)
+        strag   0(%r1),4096(%r15)
+
 #CHECK: error: offset out of range
 #CHECK: strl  %r0, -0x1000000002
 #CHECK: error: offset out of range
 #CHECK: strl  %r0, -1
 #CHECK: error: offset out of range
 #CHECK: strl  %r0, 1
 #CHECK: error: offset out of range
 #CHECK: strl  %r0, 0x100000000

test/MC/SystemZ/insn-good.s

#CHECK:  fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL
   brctg %r0, 0
 #CHECK: brctg %r0, .[[LAB:L.*]]+65534 # encoding: [0xa7,0x07,A,A]
 #CHECK:  fixup A - offset: 2, value: (.[[LAB]]+65534)+2, kind: FK_390_PC16DBL
   brctg %r0, 0xfffe
 #CHECK: brctg %r15, .[[LAB:L.*]]  # encoding: [0xa7,0xf7,A,A]
 #CHECK:  fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL
   brctg %r15, 0
 
+#CHECK: brxh  %r0, %r2, .[[LAB:L.*]]-65536  # encoding: [0x84,0x02,A,A]
+#CHECK:  fixup A - offset: 2, value: (.[[LAB]]-65536)+2, kind: FK_390_PC16DBL
+  brxh  %r0,%r2, -0x10000
+#CHECK: brxh  %r0, %r2, .[[LAB:L.*]]-2  # encoding: [0x84,0x02,A,A]
+#CHECK:  fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC16DBL
+  brxh  %r0, %r2, -2
+#CHECK: brxh  %r0, %r2, .[[LAB:L.*]]          # encoding: [0x84,0x02,A,A]
+#CHECK:  fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL
+  brxh  %r0,%r2, 0
+#CHECK: brxh  %r0, %r2, .[[LAB:L.*]]+65534  # encoding: [0x84,0x02,A,A]
+#CHECK:  fixup A - offset: 2, value: (.[[LAB]]+65534)+2, kind: FK_390_PC16DBL
+  brxh  %r0,%r2, 0xfffe
+
+#CHECK: brxh  %r0, %r2, foo                   # encoding: [0x84,0x02,A,A]
+#CHECK:  fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL
+#CHECK: brxh  %r14, %r2, foo                  # encoding: [0x84,0xe2,A,A]
+#CHECK:  fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL
+#CHECK: brxh  %r15, %r2, foo                  # encoding: [0x84,0xf2,A,A]
+#CHECK:  fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL
+  brxh  %r0,%r2,foo
+  brxh  %r14,%r2,foo
+  brxh  %r15,%r2,foo
+
+#CHECK: brxh  %r0, %r2, bar+100               # encoding: [0x84,0x02,A,A]
+#CHECK:  fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL
+#CHECK: brxh  %r14, %r2, bar+100              # encoding: [0x84,0xe2,A,A]
+#CHECK:  fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL
+#CHECK: brxh  %r15, %r2, bar+100              # encoding: [0x84,0xf2,A,A]
+#CHECK:  fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL
+  brxh  %r0,%r2,bar+100
+  brxh  %r14,%r2,bar+100
+  brxh  %r15,%r2,bar+100
+
+#CHECK: brxh  %r0, %r2, bar@PLT               # encoding: [0x84,0x02,A,A]
+#CHECK:  fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL
+#CHECK: brxh  %r14, %r2, bar@PLT              # encoding: [0x84,0xe2,A,A]
+#CHECK:  fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL
+#CHECK: brxh  %r15, %r2, bar@PLT              # encoding: [0x84,0xf2,A,A]
+#CHECK:  fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL
+  brxh  %r0,%r2,bar@PLT
+  brxh  %r14,%r2,bar@PLT
+  brxh  %r15,%r2,bar@PLT
+
+#CHECK: brxle %r0, %r2, .[[LAB:L.*]]-65536  # encoding: [0x85,0x02,A,A]
+#CHECK:  fixup A - offset: 2, value: (.[[LAB]]-65536)+2, kind: FK_390_PC16DBL
+  brxle %r0,%r2, -0x10000
+#CHECK: brxle %r0, %r2, .[[LAB:L.*]]-2  # encoding: [0x85,0x02,A,A]
+#CHECK:  fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC16DBL
+  brxle %r0, %r2, -2
+#CHECK: brxle %r0, %r2, .[[LAB:L.*]]          # encoding: [0x85,0x02,A,A]
+#CHECK:  fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL
+  brxle %r0,%r2, 0
+#CHECK: brxle %r0, %r2, .[[LAB:L.*]]+65534  # encoding: [0x85,0x02,A,A]
+#CHECK:  fixup A - offset: 2, value: (.[[LAB]]+65534)+2, kind: FK_390_PC16DBL
+  brxle %r0,%r2, 0xfffe
+
+#CHECK: brxle %r0, %r2, foo                   # encoding: [0x85,0x02,A,A]
+#CHECK:  fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL
+#CHECK: brxle %r14, %r2, foo                  # encoding: [0x85,0xe2,A,A]
+#CHECK:  fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL
+#CHECK: brxle %r15, %r2, foo                  # encoding: [0x85,0xf2,A,A]
+#CHECK:  fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL
+  brxle %r0,%r2,foo
+  brxle %r14,%r2,foo
+  brxle %r15,%r2,foo
+
+#CHECK: brxle %r0, %r2, bar+100               # encoding: [0x85,0x02,A,A]
+#CHECK:  fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL
+#CHECK: brxle %r14, %r2, bar+100              # encoding: [0x85,0xe2,A,A]
+#CHECK:  fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL
+#CHECK: brxle %r15, %r2, bar+100              # encoding: [0x85,0xf2,A,A]
+#CHECK:  fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL
+  brxle %r0,%r2,bar+100
+  brxle %r14,%r2,bar+100
+  brxle %r15,%r2,bar+100
+
+#CHECK: brxle %r0, %r2, bar@PLT               # encoding: [0x85,0x02,A,A]
+#CHECK:  fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL
+#CHECK: brxle %r14, %r2, bar@PLT              # encoding: [0x85,0xe2,A,A]
+#CHECK:  fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL
+#CHECK: brxle %r15, %r2, bar@PLT              # encoding: [0x85,0xf2,A,A]
+#CHECK:  fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL
+  brxle %r0,%r2,bar@PLT
+  brxle %r14,%r2,bar@PLT
+  brxle %r15,%r2,bar@PLT
+
 #CHECK: c %r0, 0                  # encoding: [0x59,0x00,0x00,0x00]
 #CHECK: c %r0, 4095               # encoding: [0x59,0x00,0x0f,0xff]
 #CHECK: c %r0, 0(%r1)             # encoding: [0x59,0x00,0x10,0x00]
 #CHECK: c %r0, 0(%r15)            # encoding: [0x59,0x00,0xf0,0x00]
 #CHECK: c %r0, 4095(%r1,%r15)     # encoding: [0x59,0x01,0xff,0xff]
 #CHECK: c %r0, 4095(%r15,%r1)     # encoding: [0x59,0x0f,0x1f,0xff]
 #CHECK: c %r15, 0                 # encoding: [0x59,0xf0,0x00,0x00]
 

 #CHECK: ear %r15, %a15              # encoding: [0xb2,0x4f,0x00,0xff]
 
   ear %r0, %a0
   ear %r0, %a15
   ear %r15, %a0
   ear %r7, %a8
   ear %r15, %a15
 
+#CHECK: ectg    0, 0, %r0               # encoding: [0xc8,0x01,0x00,0x00,0x00,0x00]
+#CHECK: ectg    0(%r1), 0(%r15), %r2    # encoding: [0xc8,0x21,0x10,0x00,0xf0,0x00]
+#CHECK: ectg    1(%r1), 0(%r15), %r2    # encoding: [0xc8,0x21,0x10,0x01,0xf0,0x00]
+#CHECK: ectg    4095(%r1), 0(%r15), %r2 # encoding: [0xc8,0x21,0x1f,0xff,0xf0,0x00]
+#CHECK: ectg    0(%r1), 1(%r15), %r2    # encoding: [0xc8,0x21,0x10,0x00,0xf0,0x01]
+#CHECK: ectg    0(%r1), 4095(%r15), %r2 # encoding: [0xc8,0x21,0x10,0x00,0xff,0xff]
+
+        ectg    0,0,%r0
+        ectg    0(%r1),0(%r15),%r2
+        ectg    1(%r1),0(%r15),%r2
+        ectg    4095(%r1),0(%r15),%r2
+        ectg    0(%r1),1(%r15),%r2
+        ectg    0(%r1),4095(%r15),%r2
+
 #CHECK: ex  %r0, 0                  # encoding: [0x44,0x00,0x00,0x00]
 #CHECK: ex  %r0, 4095               # encoding: [0x44,0x00,0x0f,0xff]
 #CHECK: ex  %r0, 0(%r1)             # encoding: [0x44,0x00,0x10,0x00]
 #CHECK: ex  %r0, 0(%r15)            # encoding: [0x44,0x00,0xf0,0x00]
 #CHECK: ex  %r0, 4095(%r1,%r15)     # encoding: [0x44,0x01,0xff,0xff]
 #CHECK: ex  %r0, 4095(%r15,%r1)     # encoding: [0x44,0x0f,0x1f,0xff]
 #CHECK: ex  %r15, 0                 # encoding: [0x44,0xf0,0x00,0x00]
 
#CHECK: mvc 0(256,%r15), 0          # encoding: [0xd2,0xff,0xf0,0x00,0x00,0x00]
   mvc 0(1), 4095(%r15)
   mvc 0(1,%r1), 0
   mvc 0(1,%r15), 0
   mvc 4095(1,%r1), 0
   mvc 4095(1,%r15), 0
   mvc 0(256,%r1), 0
   mvc 0(256,%r15), 0
 
+#CHECK: mvck  0(%r1), 0, %r3          # encoding: [0xd9,0x03,0x10,0x00,0x00,0x00]
+#CHECK: mvck  0(%r1), 0(%r1), %r3     # encoding: [0xd9,0x03,0x10,0x00,0x10,0x00]
+#CHECK: mvck  0(%r1), 0(%r15), %r3    # encoding: [0xd9,0x03,0x10,0x00,0xf0,0x00]
+#CHECK: mvck  0(%r1), 4095, %r3       # encoding: [0xd9,0x03,0x10,0x00,0x0f,0xff]
+#CHECK: mvck  0(%r1), 4095(%r1), %r3  # encoding: [0xd9,0x03,0x10,0x00,0x1f,0xff]
+#CHECK: mvck  0(%r1), 4095(%r15), %r3 # encoding: [0xd9,0x03,0x10,0x00,0xff,0xff]
+#CHECK: mvck  0(%r2,%r1), 0, %r3      # encoding: [0xd9,0x23,0x10,0x00,0x00,0x00]
+#CHECK: mvck  0(%r2,%r15), 0, %r3     # encoding: [0xd9,0x23,0xf0,0x00,0x00,0x00]
+#CHECK: mvck  4095(%r2,%r1), 0, %r3   # encoding: [0xd9,0x23,0x1f,0xff,0x00,0x00]
+#CHECK: mvck  4095(%r2,%r15), 0, %r3  # encoding: [0xd9,0x23,0xff,0xff,0x00,0x00]
+#CHECK: mvck  0(%r2,%r1), 0, %r3      # encoding: [0xd9,0x23,0x10,0x00,0x00,0x00]
+#CHECK: mvck  0(%r2,%r15), 0, %r3     # encoding: [0xd9,0x23,0xf0,0x00,0x00,0x00]
+
+        mvck  0(%r1), 0, %r3
+        mvck  0(%r1), 0(%r1), %r3
+        mvck  0(%r1), 0(%r15), %r3
+        mvck  0(%r1), 4095, %r3
+        mvck  0(%r1), 4095(%r1), %r3
+        mvck  0(%r1), 4095(%r15), %r3
+        mvck  0(%r2,%r1), 0, %r3
+        mvck  0(%r2,%r15), 0, %r3
+        mvck  4095(%r2,%r1), 0, %r3
+        mvck  4095(%r2,%r15), 0, %r3
+        mvck  0(%r2,%r1), 0, %r3
+        mvck  0(%r2,%r15), 0, %r3
+
 #CHECK: mvghi 0, 0                    # encoding: [0xe5,0x48,0x00,0x00,0x00,0x00]
 #CHECK: mvghi 4095, 0                 # encoding: [0xe5,0x48,0x0f,0xff,0x00,0x00]
 #CHECK: mvghi 0, -32768               # encoding: [0xe5,0x48,0x00,0x00,0x80,0x00]
 #CHECK: mvghi 0, -1                   # encoding: [0xe5,0x48,0x00,0x00,0xff,0xff]
 #CHECK: mvghi 0, 0                    # encoding: [0xe5,0x48,0x00,0x00,0x00,0x00]
 #CHECK: mvghi 0, 1                    # encoding: [0xe5,0x48,0x00,0x00,0x00,0x01]
 #CHECK: mvghi 0, 32767                # encoding: [0xe5,0x48,0x00,0x00,0x7f,0xff]
 #CHECK: mvghi 0(%r1), 42              # encoding: [0xe5,0x48,0x10,0x00,0x00,0x2a]

 #CHECK: pfdrl 7, frob@PLT           # encoding: [0xc6,0x72,A,A,A,A]
 # fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL
 #CHECK: pfdrl 8, frob@PLT           # encoding: [0xc6,0x82,A,A,A,A]
 # fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL
 
   pfdrl 7, frob@PLT
   pfdrl 8, frob@PLT
 
+#CHECK: pr                              # encoding: [0x01,0x01]
+        pr
+
 #CHECK: risbg %r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x55]
 #CHECK: risbg %r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x55]
 #CHECK: risbg %r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x55]
 #CHECK: risbg %r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x55]
 #CHECK: risbg %r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x55]
 #CHECK: risbg %r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x55]
 #CHECK: risbg %r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x55]
 
#CHECK: stmy  %r0, %r0, 524287(%r15)  # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x90]
   stmy  %r0,%r0,0
   stmy  %r0,%r0,1
   stmy  %r0,%r0,524287
   stmy  %r0,%r0,0(%r1)
   stmy  %r0,%r0,0(%r15)
   stmy  %r0,%r0,524287(%r1)
   stmy  %r0,%r0,524287(%r15)
 
+#CHECK: strag 0, 0                    # encoding: [0xe5,0x02,0x00,0x00,0x00,0x00]
+#CHECK: strag 0(%r1), 0(%r2)          # encoding: [0xe5,0x02,0x10,0x00,0x20,0x00]
+#CHECK: strag 160(%r1), 320(%r15)     # encoding: [0xe5,0x02,0x10,0xa0,0xf1,0x40]
+#CHECK: strag 0(%r1), 4095            # encoding: [0xe5,0x02,0x10,0x00,0x0f,0xff]
+#CHECK: strag 0(%r1), 4095(%r2)       # encoding: [0xe5,0x02,0x10,0x00,0x2f,0xff]
+#CHECK: strag 0(%r1), 4095(%r15)      # encoding: [0xe5,0x02,0x10,0x00,0xff,0xff]
+#CHECK: strag 0(%r1), 0               # encoding: [0xe5,0x02,0x10,0x00,0x00,0x00]
+#CHECK: strag 0(%r15), 0              # encoding: [0xe5,0x02,0xf0,0x00,0x00,0x00]
+#CHECK: strag 4095(%r1), 0            # encoding: [0xe5,0x02,0x1f,0xff,0x00,0x00]
+#CHECK: strag 4095(%r15), 0           # encoding: [0xe5,0x02,0xff,0xff,0x00,0x00]
+
+  strag 0, 0
+  strag 0(%r1), 0(%r2)
+  strag 160(%r1), 320(%r15)
+  strag 0(%r1), 4095
+  strag 0(%r1), 4095(%r2)
+  strag 0(%r1), 4095(%r15)
+  strag 0(%r1), 0
+  strag 0(%r15), 0
+  strag 4095(%r1), 0
+  strag 4095(%r15), 0
+
 #CHECK: strl  %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x0f,A,A,A,A]
 #CHECK:  fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL
   strl  %r0, -0x100000000
 #CHECK: strl  %r0, .[[LAB:L.*]]-2 # encoding: [0xc4,0x0f,A,A,A,A]
 #CHECK:  fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL
   strl  %r0, -2
 #CHECK: strl  %r0, .[[LAB:L.*]] # encoding: [0xc4,0x0f,A,A,A,A]
 #CHECK:  fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL