- User Since
- Apr 28 2016, 1:06 PM (181 w, 1 d)
Aug 18 2016
Aug 17 2016
Aug 10 2016
Aug 8 2016
Aug 5 2016
Created a custom table with operand information to parse the different formats, which calls the same parse* routines that are used by TableGen generated code.
Removed the AsmInsn* variants and allow vector registers to be recognized when parsing registers for the insn directive.
Added a comment to describe BranchBinary.
Uploaded wrong diff...
Thanks for the review Ulrich, I'll try to remember to set the right flags next time.
Aug 4 2016
Aug 3 2016
Jul 26 2016
Reworked this diff to use MC instructions to parse and emit the directive. This allows handling of PC-relative operands for some of these directives. Also added some new instructions so that we can test the .insn directive for all formats.
Jul 11 2016
Jul 8 2016
Whoops you're right, I've added ICMH to the Defs = [CC] clause.
Updated the diff with fixes based on comments, to add *Pair classes, to use InstAlias, and to remove the pattern from SLA. Also added EXRL, ICMH, STMH, LMH, and added disassembler tests.
Jul 7 2016
Jul 6 2016
Hmm, you're right, didn't notice there was an addOperand API for the builder. I've updated the diff to use addOperand instead of the specific variants.
Jun 29 2016
Once I figure out if we're sticking with this implementation, I'll continue working on this and fix up all the comments that have been made. Thanks for the quick and thorough review guys!
From my understanding, gas only supports some of the possible s390 instruction formats when using ".insn". For example, the "ri" format in the insn directive corresponds to the RI-a format, which uses an immediate field and not a relative-immediate field. Therefore, for the .insn directive specifically:
Jun 28 2016
Jun 27 2016
Jun 22 2016
Jun 10 2016
I've unmarked isTerminator from the Trap instruction for now, and removed all custom insertion code. I'll bring it up in the mailing list and see if I can't find out where it should be fixed in the common code.
Jun 9 2016
Thanks Marcin and Ulrich for the quick reviews. I've addressed most of them, and fixed the line width to 80 characters.
Jun 8 2016
May 19 2016
May 16 2016
A simple testcase is:
May 13 2016
Made changes to the diff based on Ulrich's comments:
Updated the patch to add context.
May 12 2016
Updated Bryan's patch to use the DAG combiner to combine BSWAP+LOAD to SystemZISD::LRV and STORE+BSWAP to SystemZISD::STRV, and add patterns to match these into the correct LRVH/LRV/LRVG or STRVH/STRV/STRVG opcodes.