LoadStoreVectorizer: Remove TargetBaseAlign. Keep alignment for stack adjustments.

[asbirlea]

Summary

TargetBaseAlign is no longer required since LSV checks if target allows misaligned accesses.
A constant defining a base alignment is still needed for stack accesses where alignment can be adjusted.

Previous patch (D22936) was reverted because tests were failing. This patch also fixes the cause of those failures:

• x86 failing tests either did not have the right target, or the right alignment.
• NVPTX failing tests did not have the right alignment.
• AMDGPU failing test (merge-stores) should allow vectorization with the given alignment but the target info considers <3xi32> a non-standard type and gives up early. This patch removes the condition and only checks for a maximum size allowed and relies on the next condition checking for %4 for correctness. This should be revisited to include 3xi32 as a MVT type (on arsenm's non-immediate todo list).

Note that checking the sizeInBits for a MVT is undefined (leads to an assertion failure),
so we need to create an EVT, hence the interface change in allowsMisaligned to include the Context.

[jlebar]

lib/Target/AMDGPU/SIISelLowering.cpp

451 ↗

(On Diff #66494)

We don't generally include commented-out code like this. It makes things hard to read.

In this case it's particularly hard for me to read because there are two TODOs and it's not clear how they relate to one another.

Can we have just one comment that explains where we are today and where we want to be in the future?

451 ↗

(On Diff #66494)

LLVM style is to leave off braces on single-line "if" statements. Unfortunately clang-tidy doesn't do this for you (such a waste of human time...).

479 ↗

(On Diff #66494)

I don't think you meant to include this change?

lib/Transforms/Vectorize/LoadStoreVectorizer.cpp

1038 ↗

(On Diff #66494)

Please run clang-format.

1038 ↗

(On Diff #66494)

We don't usually use {} for DEBUGs that just contain a single log statement. clang-format should be able to do something pretty here without the {}, I think.

test/Transforms/LoadStoreVectorizer/X86/preserve-order32.ll

21 ↗

(On Diff #66494)

Why the change on this line? Maybe you don't need any align for this load?

test/Transforms/LoadStoreVectorizer/X86/preserve-order64.ll

25 ↗

(On Diff #66494)

I thought x86 doesn't care about the alignment? Or, is it a question of the "fast" param?

[asbirlea]

Address comments.

[asbirlea]

test/Transforms/LoadStoreVectorizer/X86/preserve-order32.ll

21 ↗

(On Diff #66494)

This is not necessary. I can remove it completely for these 2 lines with the same outcome, but the one below for address 0 is required. I haven't looked in detail into what are the x86 requirements here.
I only changes it to 4 because it looked right considering we're using i32.

test/Transforms/LoadStoreVectorizer/X86/preserve-order64.ll

25 ↗

(On Diff #66494)

Related to the comment in the 32bit version of this, this is required for x86, haven't investigated in detail why. The other alignment directives above (buff.p and buff.val) are not needed.

[jlebar]

lgtm, but I can't speak to the correctness of the amdgpu changes, so I'd like arsenm to sign off on them.

lib/Target/AMDGPU/SIISelLowering.cpp

443 ↗

(On Diff #66512)

if the size

test/Transforms/LoadStoreVectorizer/X86/preserve-order32.ll

21 ↗

(On Diff #66494)

I only changes it to 4 because it looked right considering we're using i32.

Eh, it's x86, it doesn't really care. I'd either (a) change as little as possible, or (b) make the tests as simple as possible (removing unnecessary alignments, although e.g. if you align arr[0] to 8 bytes, saying that arr[1] is aligned to 4b doesn't seem so unreasonable).

Not a big deal, though.

test/Transforms/LoadStoreVectorizer/X86/preserve-order64.ll

25 ↗

(On Diff #66494)

It sounds like x86 is requiring us to align the whole vector. It's probably the "fast" thing. That's fine.

[asbirlea]

Address comments. Simplify tests.

[asbirlea]

test/Transforms/LoadStoreVectorizer/X86/preserve-order32.ll

21 ↗

(On Diff #66556)

I removed the alignments for arr[1] both for this and the 64bit variant of the test.

[asbirlea]

I'll wait for arsenm input on the AMD lowering changes.

[arsenm]

lib/Target/AMDGPU/SIISelLowering.cpp

444 ↗

(On Diff #66556)

Space before. Shouldn't need parentheses around the first condition. Should probably check VT.getStoreSize() > 16 (although I'm not sure that will actually matter anywhere)

[asbirlea]

Address comment.

llvm/trunk/include/llvm/Analysis/TargetTransformInfo.h

public:
   /// floating-point semantics may differ. For example, ARM NEON v7 SIMD math
   /// does not support IEEE-754 denormal numbers, while depending on the
   /// platform, scalar floating-point math does.
   /// This applies to floating-point math operations and calls, not memory
   /// operations, shuffles, or casts.
   bool isFPVectorizationPotentiallyUnsafe() const;
 
   /// \brief Determine if the target supports unaligned memory accesses.
-  bool allowsMisalignedMemoryAccesses(unsigned BitWidth, unsigned AddressSpace = 0,
+  bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
+                                      unsigned BitWidth, unsigned AddressSpace = 0,
                                       unsigned Alignment = 1,
                                       bool *Fast = nullptr) const;
 
   /// \brief Return hardware support for population count.
   PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
 
   /// \brief Return true if the hardware has a fast square-root instruction.
   bool haveFastSqrt(Type *Ty) const;
public:
   virtual bool isProfitableToHoist(Instruction *I) = 0;
   virtual bool isTypeLegal(Type *Ty) = 0;
   virtual unsigned getJumpBufAlignment() = 0;
   virtual unsigned getJumpBufSize() = 0;
   virtual bool shouldBuildLookupTables() = 0;
   virtual bool enableAggressiveInterleaving(bool LoopHasReductions) = 0;
   virtual bool enableInterleavedAccessVectorization() = 0;
   virtual bool isFPVectorizationPotentiallyUnsafe() = 0;
-  virtual bool allowsMisalignedMemoryAccesses(unsigned BitWidth,
+  virtual bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
+                                              unsigned BitWidth,
                                               unsigned AddressSpace,
                                               unsigned Alignment,
                                               bool *Fast) = 0;
   virtual PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) = 0;
   virtual bool haveFastSqrt(Type *Ty) = 0;
   virtual int getFPOpCost(Type *Ty) = 0;
   virtual int getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm,
                                     Type *Ty) = 0;
bool enableAggressiveInterleaving(bool LoopHasReductions) override {
     return Impl.enableAggressiveInterleaving(LoopHasReductions);
   }
   bool enableInterleavedAccessVectorization() override {
     return Impl.enableInterleavedAccessVectorization();
   }
   bool isFPVectorizationPotentiallyUnsafe() override {
     return Impl.isFPVectorizationPotentiallyUnsafe();
   }
-  bool allowsMisalignedMemoryAccesses(unsigned BitWidth, unsigned AddressSpace,
+  bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
+                                      unsigned BitWidth, unsigned AddressSpace,
                                       unsigned Alignment, bool *Fast) override {
-    return Impl.allowsMisalignedMemoryAccesses(BitWidth, AddressSpace,
+    return Impl.allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
                                                Alignment, Fast);
   }
   PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) override {
     return Impl.getPopcntSupport(IntTyWidthInBit);
   }
   bool haveFastSqrt(Type *Ty) override { return Impl.haveFastSqrt(Ty); }
 
   int getFPOpCost(Type *Ty) override { return Impl.getFPOpCost(Ty); }

llvm/trunk/include/llvm/Analysis/TargetTransformInfoImpl.h

public:
   bool shouldBuildLookupTables() { return true; }
 
   bool enableAggressiveInterleaving(bool LoopHasReductions) { return false; }
 
   bool enableInterleavedAccessVectorization() { return false; }
 
   bool isFPVectorizationPotentiallyUnsafe() { return false; }
 
-  bool allowsMisalignedMemoryAccesses(unsigned BitWidth,
+  bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
+                                      unsigned BitWidth,
                                       unsigned AddressSpace,
                                       unsigned Alignment,
                                       bool *Fast) { return false; }
 
   TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) {
     return TTI::PSK_Software;
   }
 

llvm/trunk/include/llvm/CodeGen/BasicTTIImpl.h

public:
   // Provide value semantics. MSVC requires that we spell all of these out.
   BasicTTIImplBase(const BasicTTIImplBase &Arg)
       : BaseT(static_cast<const BaseT &>(Arg)) {}
   BasicTTIImplBase(BasicTTIImplBase &&Arg)
       : BaseT(std::move(static_cast<BaseT &>(Arg))) {}
 
   /// \name Scalar TTI Implementations
   /// @{
-  bool allowsMisalignedMemoryAccesses(unsigned BitWidth, unsigned AddressSpace,
+  bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
+                                      unsigned BitWidth, unsigned AddressSpace,
                                       unsigned Alignment, bool *Fast) const {
-    MVT M = MVT::getIntegerVT(BitWidth);
-    return getTLI()->allowsMisalignedMemoryAccesses(M, AddressSpace, Alignment, Fast);
+    EVT E = EVT::getIntegerVT(Context, BitWidth);
+    return getTLI()->allowsMisalignedMemoryAccesses(E, AddressSpace, Alignment, Fast);
   }
 
   bool hasBranchDivergence() { return false; }
 
   bool isSourceOfDivergence(const Value *V) { return false; }
 
   bool isLegalAddImmediate(int64_t imm) {
     return getTLI()->isLegalAddImmediate(imm);

llvm/trunk/lib/Analysis/TargetTransformInfo.cpp

 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
   return TTIImpl->enableInterleavedAccessVectorization();
 }
 
 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
 }
 
-bool TargetTransformInfo::allowsMisalignedMemoryAccesses(unsigned BitWidth,
+bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
+                                                         unsigned BitWidth,
                                                          unsigned AddressSpace,
                                                          unsigned Alignment,
                                                          bool *Fast) const {
-  return TTIImpl->allowsMisalignedMemoryAccesses(BitWidth, AddressSpace,
+  return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
                                                  Alignment, Fast);
 }
 
 TargetTransformInfo::PopcntSupportKind
 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
 }
 

llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp

bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
                                                       unsigned AddrSpace,
                                                       unsigned Align,
                                                       bool *IsFast) const {
   if (IsFast)
     *IsFast = false;
 
   // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
   // which isn't a simple VT.
-  if (!VT.isSimple() || VT == MVT::Other)
+  // Until MVT is extended to handle this, simply check for the size and
+  // rely on the condition below: allow accesses if the size is a multiple of 4.
+  if (VT == MVT::Other || (VT != MVT::Other && VT.getSizeInBits() > 1024 &&
+                           VT.getStoreSize() > 16)) {
     return false;
+  }
 
   if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
       AddrSpace == AMDGPUAS::REGION_ADDRESS) {
     // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
     // aligned, 8 byte access in a single operation using ds_read2/write2_b32
     // with adjacent offsets.
     bool AlignedBy4 = (Align % 4 == 0);
     if (IsFast)

llvm/trunk/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp

 using namespace llvm;
 
 #define DEBUG_TYPE "load-store-vectorizer"
 STATISTIC(NumVectorInstructions, "Number of vector accesses generated");
 STATISTIC(NumScalarsVectorized, "Number of scalar accesses vectorized");
 
 namespace {
 
-// TODO: Remove this
-static const unsigned TargetBaseAlign = 4;
-
+// FIXME: Assuming stack alignment of 4 is always good enough
+static const unsigned StackAdjustedAlignment = 4;
 typedef SmallVector<Instruction *, 8> InstrList;
 typedef MapVector<Value *, InstrList> InstrListMap;
 
 class Vectorizer {
   Function &F;
   AliasAnalysis &AA;
   DominatorTree &DT;
   ScalarEvolution &SE;
bool Vectorizer::vectorizeStoreChain(
   if (accessIsMisaligned(SzInBytes, AS, Alignment)) {
     if (S0->getPointerAddressSpace() != 0)
       return false;
 
     // If we're storing to an object on the stack, we control its alignment,
     // so we can cheat and change it!
     Value *V = GetUnderlyingObject(S0->getPointerOperand(), DL);
     if (AllocaInst *AI = dyn_cast_or_null<AllocaInst>(V)) {
-      AI->setAlignment(TargetBaseAlign);
-      Alignment = TargetBaseAlign;
+      AI->setAlignment(StackAdjustedAlignment);
+      Alignment = StackAdjustedAlignment;
     } else {
       return false;
     }
   }
 
   BasicBlock::iterator First, Last;
   std::tie(First, Last) = getBoundaryInstrs(Chain);
   Builder.SetInsertPoint(&*Last);
bool Vectorizer::vectorizeLoadChain(
   if (accessIsMisaligned(SzInBytes, AS, Alignment)) {
     if (L0->getPointerAddressSpace() != 0)
       return false;
 
     // If we're loading from an object on the stack, we control its alignment,
     // so we can cheat and change it!
     Value *V = GetUnderlyingObject(L0->getPointerOperand(), DL);
     if (AllocaInst *AI = dyn_cast_or_null<AllocaInst>(V)) {
-      AI->setAlignment(TargetBaseAlign);
-      Alignment = TargetBaseAlign;
+      AI->setAlignment(StackAdjustedAlignment);
+      Alignment = StackAdjustedAlignment;
     } else {
       return false;
     }
   }
 
   DEBUG({
     dbgs() << "LSV: Loads to vectorize:\n";
     for (Instruction *I : Chain)
bool Vectorizer::vectorizeLoadChain(
 
   ++NumVectorInstructions;
   NumScalarsVectorized += Chain.size();
   return true;
 }
 
 bool Vectorizer::accessIsMisaligned(unsigned SzInBytes, unsigned AddressSpace,
                                     unsigned Alignment) {
+  if (Alignment % SzInBytes == 0)
+    return false;
   bool Fast = false;
-  bool Allows = TTI.allowsMisalignedMemoryAccesses(SzInBytes * 8, AddressSpace,
+  bool Allows = TTI.allowsMisalignedMemoryAccesses(F.getParent()->getContext(),
+                                                   SzInBytes * 8, AddressSpace,
                                                    Alignment, &Fast);
-  // TODO: Remove TargetBaseAlign
-  return !(Allows && Fast) && (Alignment % SzInBytes) != 0 &&
-         (Alignment % TargetBaseAlign) != 0;
+  DEBUG(dbgs() << "LSV: Target said misaligned is allowed? " << Allows
+               << " and fast? " << Fast << "\n";);
+  return !Allows || !Fast;
 }

llvm/trunk/test/Transforms/LoadStoreVectorizer/NVPTX/merge-across-side-effects.ll

 
 ; CHECK-LABEL: @load_fn
 ; CHECK: load
 ; CHECK: call void @fn()
 ; CHECK: load
 define void @load_fn(i32* %p) #0 {
   %p.1 = getelementptr i32, i32* %p, i32 1
 
-  %v0 = load i32, i32* %p
+  %v0 = load i32, i32* %p, align 8
   call void @fn()
-  %v1 = load i32, i32* %p.1
+  %v1 = load i32, i32* %p.1, align 4
   ret void
 }
 
 ; CHECK-LABEL: @load_fn_nounwind
 ; CHECK: load
 ; CHECK: call void @fn_nounwind()
 ; CHECK: load
 define void @load_fn_nounwind(i32* %p) #0 {
   %p.1 = getelementptr i32, i32* %p, i32 1
 
-  %v0 = load i32, i32* %p
+  %v0 = load i32, i32* %p, align 8
   call void @fn_nounwind() #0
-  %v1 = load i32, i32* %p.1
+  %v1 = load i32, i32* %p.1, align 4
   ret void
 }
 
 ; CHECK-LABEL: @load_fn_nounwind_writeonly
 ; CHECK: load
 ; CHECK: call void @fn_nounwind_writeonly()
 ; CHECK: load
 define void @load_fn_nounwind_writeonly(i32* %p) #0 {
   %p.1 = getelementptr i32, i32* %p, i32 1
 
-  %v0 = load i32, i32* %p
+  %v0 = load i32, i32* %p, align 8
   call void @fn_nounwind_writeonly() #1
-  %v1 = load i32, i32* %p.1
+  %v1 = load i32, i32* %p.1, align 4
   ret void
 }
 
 ; CHECK-LABEL: @load_fn_nounwind_readonly
 ; CHECK-DAG: load <2 x i32>
 ; CHECK-DAG: call void @fn_nounwind_readonly()
 define void @load_fn_nounwind_readonly(i32* %p) #0 {
   %p.1 = getelementptr i32, i32* %p, i32 1
 
-  %v0 = load i32, i32* %p
+  %v0 = load i32, i32* %p, align 8
   call void @fn_nounwind_readonly() #2
-  %v1 = load i32, i32* %p.1
+  %v1 = load i32, i32* %p.1, align 4
   ret void
 }
 
 ; CHECK-LABEL: @load_fn_readonly
 ; CHECK: load
 ; CHECK: call void @fn_readonly
 ; CHECK: load
 define void @load_fn_readonly(i32* %p) #0 {
   %p.1 = getelementptr i32, i32* %p, i32 1
 
-  %v0 = load i32, i32* %p
+  %v0 = load i32, i32* %p, align 8
   call void @fn_readonly() #4
-  %v1 = load i32, i32* %p.1
+  %v1 = load i32, i32* %p.1, align 4
   ret void
 }
 
 ; CHECK-LABEL: @load_fn_writeonly
 ; CHECK: load
 ; CHECK: call void @fn_writeonly()
 ; CHECK: load
 define void @load_fn_writeonly(i32* %p) #0 {
   %p.1 = getelementptr i32, i32* %p, i32 1
 
-  %v0 = load i32, i32* %p
+  %v0 = load i32, i32* %p, align 8
   call void @fn_writeonly() #3
-  %v1 = load i32, i32* %p.1
+  %v1 = load i32, i32* %p.1, align 4
   ret void
 }
 
 ; CHECK-LABEL: @load_fn_readnone
 ; CHECK-DAG: load <2 x i32>
 ; CHECK-DAG: call void @fn_readnone()
 define void @load_fn_readnone(i32* %p) #0 {
   %p.1 = getelementptr i32, i32* %p, i32 1
 
-  %v0 = load i32, i32* %p
+  %v0 = load i32, i32* %p, align 8
   call void @fn_readnone() #5
-  %v1 = load i32, i32* %p.1
+  %v1 = load i32, i32* %p.1, align 4
   ret void
 }
 
 ; ------------------------------------------------
 ; Same tests, but now for stores instead of loads.
 ; ------------------------------------------------
 
 ; CHECK-LABEL: @store_fn

 
 ; This is the only store idiom we can vectorize.
 ; CHECK-LABEL: @store_fn_readnone
 ; CHECK-DAG: store <2 x i32>
 ; CHECK-DAG: call void @fn_readnone()
 define void @store_fn_readnone(i32* %p) #0 {
   %p.1 = getelementptr i32, i32* %p, i32 1
 
-  store i32 0, i32* %p
+  store i32 0, i32* %p, align 8
   call void @fn_readnone() #5
-  store i32 0, i32* %p.1
+  store i32 0, i32* %p.1, align 8
   ret void
 }
 
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind writeonly }
 attributes #2 = { nounwind readonly }
 attributes #3 = { writeonly }
 attributes #4 = { readonly }
 ; readnone implies nounwind, so no need to test separately
 attributes #5 = { nounwind readnone }

llvm/trunk/test/Transforms/LoadStoreVectorizer/NVPTX/non-instr-bitcast.ll

 ; RUN: opt -mtriple=nvptx64-nvidia-cuda -load-store-vectorizer -S -o - %s | FileCheck %s
 
 ; Load from a constant.  This can be vectorized, but shouldn't crash us.
 
 @global = internal addrspace(1) constant [4 x float] [float 0xBF71111120000000, float 0x3F70410420000000, float 0xBF81111120000000, float 0x3FB5555560000000], align 4
 
 define void @foo() {
   ; CHECK: load <4 x float>
-  %a = load float, float addrspace(1)* getelementptr inbounds ([4 x float], [4 x float] addrspace(1)* @global, i64 0, i64 0), align 4
+  %a = load float, float addrspace(1)* getelementptr inbounds ([4 x float], [4 x float] addrspace(1)* @global, i64 0, i64 0), align 16
   %b = load float, float addrspace(1)* getelementptr inbounds ([4 x float], [4 x float] addrspace(1)* @global, i64 0, i64 1), align 4
   %c = load float, float addrspace(1)* getelementptr inbounds ([4 x float], [4 x float] addrspace(1)* @global, i64 0, i64 2), align 4
   %d = load float, float addrspace(1)* getelementptr inbounds ([4 x float], [4 x float] addrspace(1)* @global, i64 0, i64 3), align 4
   ret void
 }

llvm/trunk/test/Transforms/LoadStoreVectorizer/X86/correct-order.ll

-; RUN: opt -mtriple=x86-linux -load-store-vectorizer -S -o - %s | FileCheck %s
+; RUN: opt -mtriple=x86_64-unknown-linux-gnu -load-store-vectorizer -S -o - %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 
 ; CHECK-LABEL: @correct_order(
 ; CHECK: [[LOAD_PTR:%[0-9]+]] = bitcast i32* %next.gep1
 ; CHECK: load <2 x i32>, <2 x i32>* [[LOAD_PTR]]
 ; CHECK: load i32, i32* %next.gep
 ; CHECK: [[STORE_PTR:%[0-9]+]] = bitcast i32* %next.gep

llvm/trunk/test/Transforms/LoadStoreVectorizer/X86/preserve-order32.ll

 
 ; CHECK-LABEL: @preserve_order_32(
 ; CHECK: load <2 x i32>
 ; CHECK: %buff.val = load i8
 ; CHECK: store i8 0
 define void @preserve_order_32(%struct.buffer_t* noalias %buff) #0 {
 entry:
   %tmp1 = getelementptr inbounds %struct.buffer_t, %struct.buffer_t* %buff, i32 0, i32 1
-  %buff.p = load i8*, i8** %tmp1, align 8
-  %buff.val = load i8, i8* %buff.p, align 8
+  %buff.p = load i8*, i8** %tmp1
+  %buff.val = load i8, i8* %buff.p
   store i8 0, i8* %buff.p, align 8
   %tmp0 = getelementptr inbounds %struct.buffer_t, %struct.buffer_t* %buff, i32 0, i32 0
   %buff.int = load i32, i32* %tmp0, align 8
   ret void
 }
 
 attributes #0 = { nounwind }

llvm/trunk/test/Transforms/LoadStoreVectorizer/X86/preserve-order64.ll

-; RUN: opt -mtriple=x86-linux -load-store-vectorizer -S -o - %s | FileCheck %s
+; RUN: opt -mtriple=x86_64-unknown-linux-gnu -load-store-vectorizer -S -o - %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 
 %struct.buffer_t = type { i64, i8* }
 %struct.nested.buffer = type { %struct.buffer_t, %struct.buffer_t }
 
 ; Check an i64 and i8* get vectorized, and that the two accesses
 ; (load into buff.val and store to buff.p) preserve their order.
 ; Vectorized loads should be inserted at the position of the first load,
 ; and instructions which were between the first and last load should be
 ; reordered preserving their relative order inasmuch as possible.
 
 ; CHECK-LABEL: @preserve_order_64(
 ; CHECK: load <2 x i64>
 ; CHECK: %buff.val = load i8
 ; CHECK: store i8 0
 define void @preserve_order_64(%struct.buffer_t* noalias %buff) #0 {
 entry:
   %tmp1 = getelementptr inbounds %struct.buffer_t, %struct.buffer_t* %buff, i64 0, i32 1
-  %buff.p = load i8*, i8** %tmp1, align 8
-  %buff.val = load i8, i8* %buff.p, align 8
+  %buff.p = load i8*, i8** %tmp1
+  %buff.val = load i8, i8* %buff.p
   store i8 0, i8* %buff.p, align 8
   %tmp0 = getelementptr inbounds %struct.buffer_t, %struct.buffer_t* %buff, i64 0, i32 0
-  %buff.int = load i64, i64* %tmp0, align 8
+  %buff.int = load i64, i64* %tmp0, align 16
   ret void
 }
 
 ; Check reordering recurses correctly.
 
 ; CHECK-LABEL: @transitive_reorder(
 ; CHECK: load <2 x i64>
 ; CHECK: %buff.val = load i8
 ; CHECK: store i8 0
 define void @transitive_reorder(%struct.buffer_t* noalias %buff, %struct.nested.buffer* noalias %nest) #0 {
 entry:
   %nest0_0 = getelementptr inbounds %struct.nested.buffer, %struct.nested.buffer* %nest, i64 0, i32 0
   %tmp1 = getelementptr inbounds %struct.buffer_t, %struct.buffer_t* %nest0_0, i64 0, i32 1
-  %buff.p = load i8*, i8** %tmp1, align 8
-  %buff.val = load i8, i8* %buff.p, align 8
+  %buff.p = load i8*, i8** %tmp1
+  %buff.val = load i8, i8* %buff.p
   store i8 0, i8* %buff.p, align 8
   %nest1_0 = getelementptr inbounds %struct.nested.buffer, %struct.nested.buffer* %nest, i64 0, i32 0
   %tmp0 = getelementptr inbounds %struct.buffer_t, %struct.buffer_t* %nest1_0, i64 0, i32 0
-  %buff.int = load i64, i64* %tmp0, align 8
+  %buff.int = load i64, i64* %tmp0, align 16
   ret void
 }
 
 ; Check for no vectorization over phi node
 
 ; CHECK-LABEL: @no_vect_phi(
 ; CHECK: load i8*
 ; CHECK: load i8
 ; CHECK: store i8 0
 ; CHECK: load i64
 define void @no_vect_phi(i32* noalias %ptr, %struct.buffer_t* noalias %buff) {
 entry:
   %tmp1 = getelementptr inbounds %struct.buffer_t, %struct.buffer_t* %buff, i64 0, i32 1
-  %buff.p = load i8*, i8** %tmp1, align 8
-  %buff.val = load i8, i8* %buff.p, align 8
+  %buff.p = load i8*, i8** %tmp1
+  %buff.val = load i8, i8* %buff.p
   store i8 0, i8* %buff.p, align 8
   br label %"for something"
 
 "for something":
   %index = phi i64 [ 0, %entry ], [ %index.next, %"for something" ]
 
   %tmp0 = getelementptr inbounds %struct.buffer_t, %struct.buffer_t* %buff, i64 0, i32 0
-  %buff.int = load i64, i64* %tmp0, align 8
+  %buff.int = load i64, i64* %tmp0, align 16
 
   %index.next = add i64 %index, 8
   %cmp_res = icmp eq i64 %index.next, 8
   br i1 %cmp_res, label %ending, label %"for something"
 
 ending:
   ret void
 }
 
 attributes #0 = { nounwind }

llvm/trunk/test/Transforms/LoadStoreVectorizer/X86/subchain-interleaved.ll

-; RUN: opt -mtriple=x86-linux -load-store-vectorizer -S -o - %s | FileCheck %s
+; RUN: opt -mtriple=x86_64-unknown-linux-gnu -load-store-vectorizer -S -o - %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 
 ; Vectorized subsets of the load/store chains in the presence of
 ; interleaved loads/stores
 
 ; CHECK-LABEL: @interleave_2L_2S(
 ; CHECK: load <2 x i32>