AArch64: Add missing branch relaxation tests

[arsenm]

Summary

The branch relaxation pass has the worst test coverage
of any pass in AArch64. Add a few tests that hit some
large pieces of code in the pass.

http://llvm.org/reports/coverage/lib/Target/AArch64/AArch64BranchRelaxation.cpp.gcov.html

[rovka]

Thanks for working on this. Could you please rename the test files to branch-relax-blah.ll? (To match the already-existing branch-relax-asm.ll).

lib/Target/AArch64/AArch64InstrInfo.cpp

134

I'd rather move this closer to the point of use, because that would make the need for it clearer. But that's just personal preference.

[arsenm]

lib/Target/AArch64/AArch64InstrInfo.cpp

134

Do you mean into the pass itself?

[arsenm]

lib/Target/AArch64/AArch64InstrInfo.cpp

134

I'm trying to move the target specific details out of the pass, to I don't think it should go there

[rovka]

lib/Target/AArch64/AArch64InstrInfo.cpp

134

No, I guess the pass itself is too far off, and it's probably just as well if it lives here or in isBranchInRange. LGTM as it is, thanks.

[arsenm]

Test in r277428, splitting the assert to a later patch

lib/Target/AArch64/AArch64InstrInfo.cpp

 }
 
 static unsigned getBranchMaxDisplacementBytes(unsigned Opc) {
   if (Opc == AArch64::B)
     return -1;
 
   unsigned Bits = getBranchDisplacementBits(Opc);
   unsigned MaxOffs = ((1 << (Bits - 1)) - 1) << 2;
+
+  // Verify the displacement bits options have sane values.
+  // XXX: Is there a better place for this?
+  assert(MaxOffs >= 8 &&
+         "max branch displacement must be enough to jump"
+         "over conditional branch expansion");
+
   return MaxOffs;
 }
 
 bool AArch64InstrInfo::isBranchInRange(unsigned BranchOp, uint64_t BrOffset,
                                        uint64_t DestOffset) const {
   unsigned MaxOffs = getBranchMaxDisplacementBytes(BranchOp);
 
   // Branch before the Dest.

test/CodeGen/AArch64/relax-branch-bcc.ll

+; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-bcc-offset-bits=3 < %s | FileCheck %s
+
+; CHECK-LABEL: invert_bcc:
+; CHECK:       fcmp s0, s1
+; CHECK-NEXT:  b.ne [[BB1:LBB[0-9]+_[0-9]+]]
+; CHECK-NEXT:  b.vs [[BB2:LBB[0-9]+_[0-9]+]]
+; CHECK-NEXT:  b [[BB2]]
+
+; CHECK: [[BB1]]:
+; CHECK: mov w{{[0-9]+}}, #9
+; CHECK: ret
+
+; CHECK: [[BB2]]:
+; CHECK: mov w{{[0-9]+}}, #42
+; CHECK: ret
+
+define i32 @invert_bcc(float %x, float %y) #0 {
+  %1 = fcmp ueq float %x, %y
+  br i1 %1, label %bb1, label %bb2
+
+bb2:
+  call void asm sideeffect
+    "nop
+     nop",
+    ""() #0
+  store volatile i32 9, i32* undef
+  ret i32 1
+
+bb1:
+  store volatile i32 42, i32* undef
+  ret i32 0
+}
+
+declare i32 @foo() #0
+
+; CHECK-LABEL: _block_split:
+; CHECK: cmp w0, #5
+; CHECK-NEXT: b.eq [[LONG_BR_BB:LBB[0-9]+_[0-9]+]]
+; CHECK-NEXT: b [[LOR_LHS_FALSE_BB:LBB[0-9]+_[0-9]+]]
+
+; CHECK: [[LONG_BR_BB]]:
+; CHECK-NEXT: b [[IF_THEN_BB:LBB[0-9]+_[0-9]+]]
+
+; CHECK: [[LOR_LHS_FALSE_BB]]:
+; CHECK: cmp w{{[0-9]+}}, #16
+; CHECK-NEXT: b.le [[IF_THEN_BB]]
+; CHECK-NEXT: b [[IF_END_BB:LBB[0-9]+_[0-9]+]]
+
+; CHECK: [[IF_THEN_BB]]:
+; CHECK: bl _foo
+; CHECK-NOT: b L
+
+; CHECK: [[IF_END_BB]]:
+; CHECK: #0x7
+; CHECK: ret
+define i32 @block_split(i32 %a, i32 %b) #0 {
+entry:
+  %cmp = icmp eq i32 %a, 5
+  br i1 %cmp, label %if.then, label %lor.lhs.false
+
+lor.lhs.false:                                    ; preds = %entry
+  %cmp1 = icmp slt i32 %b, 7
+  %mul = shl nsw i32 %b, 1
+  %add = add nsw i32 %b, 1
+  %cond = select i1 %cmp1, i32 %mul, i32 %add
+  %cmp2 = icmp slt i32 %cond, 17
+  br i1 %cmp2, label %if.then, label %if.end
+
+if.then:                                          ; preds = %lor.lhs.false, %entry
+  %call = tail call i32 @foo()
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %lor.lhs.false
+  ret i32 7
+}
+
+attributes #0 = { nounwind }

test/CodeGen/AArch64/relax-branch-cbz.ll

+; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-cbz-offset-bits=3 < %s | FileCheck %s
+
+; CHECK-LABEL: _split_block_no_fallthrough:
+; CHECK: cmn x{{[0-9]+}}, #5
+; CHECK-NEXT: b.le [[B2:LBB[0-9]+_[0-9]+]]
+
+; CHECK-NEXT: ; BB#1: ; %b3
+; CHECK: ldr [[LOAD:w[0-9]+]]
+; CHECK: cbz [[LOAD]], [[SKIP_LONG_B:LBB[0-9]+_[0-9]+]]
+; CHECK-NEXT: b [[B8:LBB[0-9]+_[0-9]+]]
+
+; CHECK-NEXT: [[SKIP_LONG_B]]:
+; CHECK-NEXT: b [[B7:LBB[0-9]+_[0-9]+]]
+
+; CHECK-NEXT: [[B2]]: ; %b2
+; CHECK: mov w{{[0-9]+}}, #93
+; CHECK: bl _extfunc
+; CHECK: cbz w{{[0-9]+}}, [[B7]]
+
+; CHECK-NEXT: [[B8]]: ; %b8
+; CHECK-NEXT: ret
+
+; CHECK-NEXT: [[B7]]: ; %b7
+; CHECK: mov w{{[0-9]+}}, #13
+; CHECK: b _extfunc
+define void @split_block_no_fallthrough(i64 %val) #0 {
+bb:
+  %c0 = icmp sgt i64 %val, -5
+  br i1 %c0, label %b3, label %b2
+
+b2:
+  %v0 = tail call i32 @extfunc(i32 93)
+  %c1 = icmp eq i32 %v0, 0
+  br i1 %c1, label %b7, label %b8
+
+b3:
+  %v1 = load volatile i32, i32* undef, align 4
+  %c2 = icmp eq i32 %v1, 0
+  br i1 %c2, label %b7, label %b8
+
+b7:
+  %tmp1 = tail call i32 @extfunc(i32 13)
+  ret void
+
+b8:
+  ret void
+}
+
+declare i32 @extfunc(i32) #0
+
+attributes #0 = { nounwind }