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Differential D22466

Avoid false dependencies of undef machine operands
ClosedPublic

Authored by myatsina on Jul 18 2016, 9:30 AM.

Details

Reviewers
spatel
danielcdh
atrick
mkuper
Commits
rG88f0c31f13d6: Avoid false dependencies of undef machine operands
rL278321: Avoid false dependencies of undef machine operands
Summary

This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with the largest clearance.

Pseudo example:

loop:
xmm0 = ...
xmm1 = vcvtsi2sdl eax, xmm0<undef>
... = inst xmm0
jmp loop

In this example, selecting xmm0 as the undef register creates false dependency between loop iterations.
This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction.
Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem.

Diff Detail

Repository
rL LLVM

Event Timeline

myatsina updated this revision to Diff 64335.Jul 18 2016, 9:30 AM
myatsina retitled this revision from to Avoid false dependencies of undef machine operands.
myatsina updated this object.
myatsina added reviewers: atrick, danielcdh, mkuper, spatel.
myatsina set the repository for this revision to rL LLVM.
myatsina added subscribers: llvm-commits, DavidKreitzer.
myatsina retitled this revision from Avoid false dependencies of undef machine operands to Avoid false dependencies of undef machine operands + fix bug in clearance calculation.Jul 18 2016, 9:33 AM
myatsina updated this object.
myatsina added inline comments.
lib/CodeGen/ExecutionDepsFix.cpp
523

This is a fix to bug - the clearance calculation did not take into account registers defined as outputs or clobbers in inline assembly machine instructions because these register defs are implicit.

mkuper added inline comments.Jul 19 2016, 5:28 PM
lib/CodeGen/ExecutionDepsFix.cpp
486

I'm a bit confused about this condition. Could you explain?

492

Why not a range for over MI->operands()?

503

This happens only when the real input operand is in memory, right?
If so, is this better than undoing the load folding, and using the loaded register as undef? Or does that depend on the clearance / being able to xor the register?

(This patch looks like a a net improvement regardless, I'm wondering about a possible TODO/follow-up patch)

511

Can we break if we've passed the "minimum required clearance" (that is, Pref)?

523

Any reason not to commit this separately?

myatsina marked 2 inline comments as done.Jul 21 2016, 9:48 AM
myatsina added inline comments.
lib/CodeGen/ExecutionDepsFix.cpp
486

Commit 224447 by Matthias Braun added some ARM specific fix that allows one register to be mapped to several registers from the register class (for ARM a wider register like Q0 can be mapped to several consecutive D registers).
Before his commit the Q register was mapped to the last D register of the sequence.
I want to avoid these cases where one register can be mapped to several registers because in these cases I cannot replace the original register in the instruction.

503

This catches cases like this:
vcvtsi2ssl %eax, %xmm0, %xmm1
This instruction does not have a form with xmm as a source.
"CVTDQ2PS %xmm0, %xmm1" is the packed version of the instruction.
Are you suggesting that if I see something like:
vpextrl $1, %xmm0, %eax
vcvtsi2ssl %eax, %xmm1, %xmm1
I should replace it with
CVTDQ2PS %xmm0, %xmm1 ?

BTW, I think one possible (and probably rare) follow up is handling cases where the register with the highest clearance is alive (and therefore we cannot add an xor), while we have another register, with lower clearance, that is not alive. In this case we should make a smarter decision regarding which one to choose.

511

I've measured both options, and choosing a register with max clearance gives slightly better results than choosing a register with clearance > Pref.

523

https://reviews.llvm.org/D22580

myatsina updated this revision to Diff 64950.Jul 21 2016, 1:40 PM
myatsina retitled this revision from Avoid false dependencies of undef machine operands + fix bug in clearance calculation to Avoid false dependencies of undef machine operands.
myatsina updated this object.
myatsina marked an inline comment as done.
mkuper added inline comments.Jul 21 2016, 5:35 PM
lib/CodeGen/ExecutionDepsFix.cpp
486

Ok. I'm still not sure I understand exactly what's going on, but it's ok to be conservative - especially since right now we should never hit this anyway. We only exercise this code path for X86 (I believe it's the only in-tree backend that actually implements getUndefRegClearance()), and if this is ARM-specific, then it doesn't really matter...

503

No, not what I meant, and in any case, it was not a good idea, ignore my comment. :-)

511

We could treat that as an indication that Pref isn't high enough - see the discussion on D21560.
If you have experimental evidence that increasing Pref to, say, 96 or 128, increases performance (above the noise level), then we should do that. Otherwise, we should probably bail on Pref here as well. I don't think it makes sense to be inconsistent about it.

myatsina updated this revision to Diff 66280.Aug 1 2016, 12:11 AM

Update code using clearance > Pref..
Updated Pref to 128. My runs show it's slightly better than 64.

myatsina marked an inline comment as done.Aug 1 2016, 12:13 AM
mkuper accepted this revision.Aug 1 2016, 11:00 AM
mkuper edited edge metadata.

LGTM, after you add (or document) the possibly missing test.

lib/CodeGen/ExecutionDepsFix.cpp
499

Do we have a test-case where we expect this to happen?
If we don't, can you add one? If we do, can you clearly document it as such?

This revision is now accepted and ready to land.Aug 1 2016, 11:00 AM
myatsina updated this revision to Diff 67351.Aug 9 2016, 8:19 AM
myatsina edited edge metadata.
  1. Added a test for the case of true dependency.
  2. Fixed a bug in my code exposed by Craig Topper's commit #276393 - some of my lit tests started to fail after his change because I was using the register class that was passed in ExeDepsFix's constructor instead of using the register class of the actual machine instruction operand I want to replace.
  3. Fixed additional tests that were added I the meantime.
myatsina marked an inline comment as done.Aug 9 2016, 8:21 AM
myatsina added inline comments.
lib/CodeGen/ExecutionDepsFix.cpp
491

This is a bug fixed exposed by Craig Topper's commit #276393.
Now using the register class of the actual machine instruction operand I want to replace.

mkuper added inline comments.Aug 9 2016, 9:57 AM
lib/CodeGen/ExecutionDepsFix.cpp
491

This looks a bit weird.
It would probably be better to use MRI->getRegClass(OriginalReg).
(We already query MachineRegisterInfo in runOnFunction, you can convert that to a member)

myatsina added inline comments.Aug 10 2016, 2:20 AM
lib/CodeGen/ExecutionDepsFix.cpp
491

MRI->getRegClass() receives a virtual reg, but I do not have access to virtual regs in this pass.
How about "TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF)"?
This seems to work as well.

mkuper added inline comments.Aug 10 2016, 9:57 AM
lib/CodeGen/ExecutionDepsFix.cpp
491

Gah, you're right, sorry.
Anyway, yes, I think I'd prefer TII->getRegClass.

Closed by commit rL278321: Avoid false dependencies of undef machine operands (authored by myatsina). · Explain WhyAug 11 2016, 12:40 AM
This revision was automatically updated to reflect the committed changes.
MatzeB added a subscriber: MatzeB.Oct 28 2016, 2:45 PM
MatzeB added inline comments.
llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
492–494 ↗(On Diff #67658)

getRegClass() can return nullptr if there is not register class declared/defined in MCInstrDesc (happens mostly on generic instructions like COPY or INLINEASM). The code looks like it would crash in this case.

499 ↗(On Diff #67658)

I would use !CurrMO.readsReg() instead of isUndef(), that way bundle internal reads are ignored as well.

512 ↗(On Diff #67658)

This looks bogus if OpRC is ever != ExeDepsFix::RC. Maybe you shouldn't even query OpRC and use ExeDepsFix::RC? Or can there be situations in which an operand has a restricted register class?

523–525 ↗(On Diff #67658)

If multiple operands use the same register, they all need to be updated at the same time (MachineOperand documents that even for undef inputs with the same register read the same value).

Revision Contents

PathSize
lib/
CodeGen/
47 lines
test/
CodeGen/
X86/
51 lines
3 lines
2 lines
294 lines

Diff 64335

lib/CodeGen/ExecutionDepsFix.cpp

Show First 20 Lines • Show All 197 Lines • ▼ Show 20 Linesprivate:
bool merge(DomainValue *A, DomainValue *B); bool merge(DomainValue *A, DomainValue *B);
void enterBasicBlock(MachineBasicBlock*); void enterBasicBlock(MachineBasicBlock*);
void leaveBasicBlock(MachineBasicBlock*); void leaveBasicBlock(MachineBasicBlock*);
void visitInstr(MachineInstr*); void visitInstr(MachineInstr*);
void processDefs(MachineInstr*, bool Kill); void processDefs(MachineInstr*, bool Kill);
void visitSoftInstr(MachineInstr*, unsigned mask); void visitSoftInstr(MachineInstr*, unsigned mask);
void visitHardInstr(MachineInstr*, unsigned domain); void visitHardInstr(MachineInstr*, unsigned domain);
void pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx);
bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref); bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
void processUndefReads(MachineBasicBlock*); void processUndefReads(MachineBasicBlock*);
}; };
} }
char ExeDepsFix::ID = 0; char ExeDepsFix::ID = 0;
/// Translate TRI register number to a list of indices into our smaller tables /// Translate TRI register number to a list of indices into our smaller tables
▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Lines else
visitHardInstr(MI, DomP.first); visitHardInstr(MI, DomP.first);
} }
// Process defs to track register ages, and kill values clobbered by generic // Process defs to track register ages, and kill values clobbered by generic
// instructions. // instructions.
processDefs(MI, !DomP.first); processDefs(MI, !DomP.first);
} }
/// \brief Helps avoid false dependencies on undef registers by updating the
/// machine instructions' undef operand to use a register that the instruction
/// is truly dependent on, or use a register with the largest clearance.
void ExeDepsFix::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx) {
MachineOperand &MO = MI->getOperand(OpIdx);
assert(MO.isUndef() && "Expected undef machine operand");
unsigned OriginalReg = MO.getReg();
// Update only undef operands that are mapped to one register.
mkuperUnsubmitted
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I'm a bit confused about this condition. Could you explain?

mkuper: I'm a bit confused about this condition. Could you explain?
myatsinaAuthorUnsubmitted
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Commit 224447 by Matthias Braun added some ARM specific fix that allows one register to be mapped to several registers from the register class (for ARM a wider register like Q0 can be mapped to several consecutive D registers).
Before his commit the Q register was mapped to the last D register of the sequence.
I want to avoid these cases where one register can be mapped to several registers because in these cases I cannot replace the original register in the instruction.

myatsina: Commit 224447 by Matthias Braun added some ARM specific fix that allows one register to be…
mkuperUnsubmitted
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Ok. I'm still not sure I understand exactly what's going on, but it's ok to be conservative - especially since right now we should never hit this anyway. We only exercise this code path for X86 (I believe it's the only in-tree backend that actually implements getUndefRegClearance()), and if this is ARM-specific, then it doesn't really matter...

mkuper: Ok. I'm still not sure I understand exactly what's going on, but it's ok to be conservative…
if (AliasMap[OriginalReg].size() != 1)
return;
// If the instruction has a true dependency, we can hide the false depdency
// behind it.
myatsinaAuthorUnsubmitted
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This is a bug fixed exposed by Craig Topper's commit #276393.
Now using the register class of the actual machine instruction operand I want to replace.

myatsina: This is a bug fixed exposed by Craig Topper's commit #276393. Now using the register class of…
mkuperUnsubmitted
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This looks a bit weird.
It would probably be better to use MRI->getRegClass(OriginalReg).
(We already query MachineRegisterInfo in runOnFunction, you can convert that to a member)

mkuper: This looks a bit weird. It would probably be better to use MRI->getRegClass(OriginalReg). (We…
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MRI->getRegClass() receives a virtual reg, but I do not have access to virtual regs in this pass.
How about "TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF)"?
This seems to work as well.

myatsina: MRI->getRegClass() receives a virtual reg, but I do not have access to virtual regs in this…
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Gah, you're right, sorry.
Anyway, yes, I think I'd prefer TII->getRegClass.

mkuper: Gah, you're right, sorry. Anyway, yes, I think I'd prefer TII->getRegClass.
for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
mkuperUnsubmitted
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Why not a range for over MI->operands()?

mkuper: Why not a range for over MI->operands()?
MachineOperand &CurrMO = MI->getOperand(i);
if (!CurrMO.isReg() || CurrMO.isDef() || CurrMO.isUndef() ||
!RC->contains(CurrMO.getReg()))
continue;
// We found a true dependency - replace the undef register with the true
// dependency.
MO.setReg(CurrMO.getReg());
mkuperUnsubmitted
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Do we have a test-case where we expect this to happen?
If we don't, can you add one? If we do, can you clearly document it as such?

mkuper: Do we have a test-case where we expect this to happen? If we don't, can you add one? If we do…
return;
}
// Go over all registers in the register class and find the register with the
mkuperUnsubmitted
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This happens only when the real input operand is in memory, right?
If so, is this better than undoing the load folding, and using the loaded register as undef? Or does that depend on the clearance / being able to xor the register?

(This patch looks like a a net improvement regardless, I'm wondering about a possible TODO/follow-up patch)

mkuper: This happens only when the real input operand is in memory, right? If so, is this better than…
myatsinaAuthorUnsubmitted
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This catches cases like this:
vcvtsi2ssl %eax, %xmm0, %xmm1
This instruction does not have a form with xmm as a source.
"CVTDQ2PS %xmm0, %xmm1" is the packed version of the instruction.
Are you suggesting that if I see something like:
vpextrl $1, %xmm0, %eax
vcvtsi2ssl %eax, %xmm1, %xmm1
I should replace it with
CVTDQ2PS %xmm0, %xmm1 ?

BTW, I think one possible (and probably rare) follow up is handling cases where the register with the highest clearance is alive (and therefore we cannot add an xor), while we have another register, with lower clearance, that is not alive. In this case we should make a smarter decision regarding which one to choose.

myatsina: This catches cases like this: vcvtsi2ssl %eax, %xmm0, %xmm1 This instruction does not have a…
mkuperUnsubmitted
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No, not what I meant, and in any case, it was not a good idea, ignore my comment. :-)

mkuper: No, not what I meant, and in any case, it was not a good idea, ignore my comment. :-)
// max clearance.
unsigned MaxClearance = 0;
unsigned MaxClearanceReg = OriginalReg;
for (unsigned rx = 0; rx < NumRegs; ++rx) {
unsigned Clearance = CurInstr - LiveRegs[rx].Def;
if (Clearance <= MaxClearance)
continue;
MaxClearance = Clearance;
mkuperUnsubmitted
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Can we break if we've passed the "minimum required clearance" (that is, Pref)?

mkuper: Can we break if we've passed the "minimum required clearance" (that is, Pref)?
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I've measured both options, and choosing a register with max clearance gives slightly better results than choosing a register with clearance > Pref.

myatsina: I've measured both options, and choosing a register with max clearance gives slightly better…
mkuperUnsubmitted
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We could treat that as an indication that Pref isn't high enough - see the discussion on D21560.
If you have experimental evidence that increasing Pref to, say, 96 or 128, increases performance (above the noise level), then we should do that. Otherwise, we should probably bail on Pref here as well. I don't think it makes sense to be inconsistent about it.

mkuper: We could treat that as an indication that Pref isn't high enough - see the discussion on D21560.
MaxClearanceReg = RC->getRegister(rx);
}
// Update the operand if we found a register with better clearance.
if (MaxClearanceReg != OriginalReg)
MO.setReg(MaxClearanceReg);
}
/// \brief Return true to if it makes sense to break dependence on a partial def /// \brief Return true to if it makes sense to break dependence on a partial def
/// or undef use. /// or undef use.
bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
unsigned Pref) { unsigned Pref) {
unsigned reg = MI->getOperand(OpIdx).getReg(); unsigned reg = MI->getOperand(OpIdx).getReg();
for (int rx : regIndices(reg)) { for (int rx : regIndices(reg)) {
unsigned Clearance = CurInstr - LiveRegs[rx].Def; unsigned Clearance = CurInstr - LiveRegs[rx].Def;
DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref); DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref);
Show All 21 Lines
// Also break dependencies on partial defs and undef uses. // Also break dependencies on partial defs and undef uses.
void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) { void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) {
assert(!MI->isDebugValue() && "Won't process debug values"); assert(!MI->isDebugValue() && "Won't process debug values");
// Break dependence on undef uses. Do this before updating LiveRegs below. // Break dependence on undef uses. Do this before updating LiveRegs below.
unsigned OpNum; unsigned OpNum;
unsigned Pref = TII->getUndefRegClearance(*MI, OpNum, TRI); unsigned Pref = TII->getUndefRegClearance(*MI, OpNum, TRI);
if (Pref) { if (Pref) {
pickBestRegisterForUndef(MI, OpNum);
if (shouldBreakDependence(MI, OpNum, Pref)) if (shouldBreakDependence(MI, OpNum, Pref))
UndefReads.push_back(std::make_pair(MI, OpNum)); UndefReads.push_back(std::make_pair(MI, OpNum));
} }
const MCInstrDesc &MCID = MI->getDesc(); const MCInstrDesc &MCID = MI->getDesc();
for (unsigned i = 0, for (unsigned i = 0,
e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
i != e; ++i) { i != e; ++i) {
MachineOperand &MO = MI->getOperand(i); MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg()) if (!MO.isReg())
continue; continue;
if (MO.isImplicit())
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This is a fix to bug - the clearance calculation did not take into account registers defined as outputs or clobbers in inline assembly machine instructions because these register defs are implicit.

myatsina: This is a fix to bug - the clearance calculation did not take into account registers defined as…
mkuperUnsubmitted
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Any reason not to commit this separately?

mkuper: Any reason not to commit this separately?
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https://reviews.llvm.org/D22580

myatsina: https://reviews.llvm.org/D22580
break;
if (MO.isUse()) if (MO.isUse())
continue; continue;
for (int rx : regIndices(MO.getReg())) { for (int rx : regIndices(MO.getReg())) {
// This instruction explicitly defines rx. // This instruction explicitly defines rx.
DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
<< '\t' << *MI); << '\t' << *MI);
// Check clearance before partial register updates. // Check clearance before partial register updates.
▲ Show 20 Lines • Show All 279 Lines • Show Last 20 Lines

test/CodeGen/X86/break-false-dep.ll

Show First 20 Lines • Show All 120 Lines • ▼ Show 20 Lines
define i64 @loopdep2(i64* nocapture %x, double* nocapture %y) nounwind { define i64 @loopdep2(i64* nocapture %x, double* nocapture %y) nounwind {
entry: entry:
%vx = load i64, i64* %x %vx = load i64, i64* %x
br label %loop br label %loop
loop: loop:
%i = phi i64 [ 1, %entry ], [ %inc, %loop ] %i = phi i64 [ 1, %entry ], [ %inc, %loop ]
%s1 = phi i64 [ %vx, %entry ], [ %s2, %loop ] %s1 = phi i64 [ %vx, %entry ], [ %s2, %loop ]
%fi = sitofp i64 %i to double %fi = sitofp i64 %i to double
tail call void asm sideeffect "", "~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"()
%vy = load double, double* %y %vy = load double, double* %y
%fipy = fadd double %fi, %vy %fipy = fadd double %fi, %vy
%iipy = fptosi double %fipy to i64 %iipy = fptosi double %fipy to i64
%s2 = add i64 %s1, %iipy %s2 = add i64 %s1, %iipy
%inc = add nsw i64 %i, 1 %inc = add nsw i64 %i, 1
%exitcond = icmp eq i64 %inc, 156250000 %exitcond = icmp eq i64 %inc, 156250000
br i1 %exitcond, label %ret, label %loop br i1 %exitcond, label %ret, label %loop
ret: ret:
Show All 32 Linesfor.body3:
%mul8 = fmul double %mul, %2 %mul8 = fmul double %mul, %2
%arrayidx10 = getelementptr inbounds [1024 x double], [1024 x double]* @z, i64 0, i64 %indvars.iv %arrayidx10 = getelementptr inbounds [1024 x double], [1024 x double]* @z, i64 0, i64 %indvars.iv
%3 = load double, double* %arrayidx10, align 8 %3 = load double, double* %arrayidx10, align 8
%mul11 = fmul double %mul8, %3 %mul11 = fmul double %mul8, %3
%arrayidx13 = getelementptr inbounds [1024 x double], [1024 x double]* @w, i64 0, i64 %indvars.iv %arrayidx13 = getelementptr inbounds [1024 x double], [1024 x double]* @w, i64 0, i64 %indvars.iv
store double %mul11, double* %arrayidx13, align 8 store double %mul11, double* %arrayidx13, align 8
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%exitcond = icmp eq i64 %indvars.iv.next, 1024 %exitcond = icmp eq i64 %indvars.iv.next, 1024
tail call void asm sideeffect "", "~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"()
br i1 %exitcond, label %for.inc14, label %for.body3 br i1 %exitcond, label %for.inc14, label %for.body3
for.inc14: ; preds = %for.body3 for.inc14: ; preds = %for.body3
%inc15 = add nsw i32 %i.025, 1 %inc15 = add nsw i32 %i.025, 1
%exitcond26 = icmp eq i32 %inc15, 100000 %exitcond26 = icmp eq i32 %inc15, 100000
br i1 %exitcond26, label %for.end16, label %for.cond1.preheader br i1 %exitcond26, label %for.end16, label %for.cond1.preheader
for.end16: ; preds = %for.inc14 for.end16: ; preds = %for.inc14
ret void ret void
;SSE-LABEL:@loopdep3 ;SSE-LABEL:@loopdep3
;SSE: xorps [[XMM0:%xmm[0-9]+]], [[XMM0]] ;SSE: xorps [[XMM0:%xmm[0-9]+]], [[XMM0]]
;SSE-NEXT: cvtsi2sdl {{.*}}, [[XMM0]] ;SSE-NEXT: cvtsi2sdl {{.*}}, [[XMM0]]
;SSE-NEXT: mulsd {{.*}}, [[XMM0]] ;SSE-NEXT: mulsd {{.*}}, [[XMM0]]
;SSE-NEXT: mulsd {{.*}}, [[XMM0]] ;SSE-NEXT: mulsd {{.*}}, [[XMM0]]
;SSE-NEXT: mulsd {{.*}}, [[XMM0]] ;SSE-NEXT: mulsd {{.*}}, [[XMM0]]
;SSE-NEXT: movsd [[XMM0]], ;SSE-NEXT: movsd [[XMM0]],
;AVX-LABEL:@loopdep3 ;AVX-LABEL:@loopdep3
;AVX: vxorps [[XMM0:%xmm[0-9]+]], [[XMM0]] ;AVX: vxorps [[XMM0:%xmm[0-9]+]], [[XMM0]]
;AVX-NEXT: vcvtsi2sdl {{.*}}, [[XMM0]], [[XMM0]] ;AVX-NEXT: vcvtsi2sdl {{.*}}, [[XMM0]], {{%xmm[0-9]+}}
;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]] ;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]] ;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]] ;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
;AVX-NEXT: vmovsd [[XMM0]], ;AVX-NEXT: vmovsd [[XMM0]],
} }
; Make sure we are making a smart choice regarding undef registers and
; choosing the register with the highest clearence
define double @clearence(i64 %arg) {
top:
tail call void asm sideeffect "", "~{xmm6},~{dirflag},~{fpsr},~{flags}"()
tail call void asm sideeffect "", "~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{dirflag},~{fpsr},~{flags}"()
tail call void asm sideeffect "", "~{xmm4},~{xmm5},~{xmm7},~{dirflag},~{fpsr},~{flags}"()
tail call void asm sideeffect "", "~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{dirflag},~{fpsr},~{flags}"()
tail call void asm sideeffect "", "~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"()
%tmp1 = sitofp i64 %arg to double
ret double %tmp1
;AVX-LABEL:@clearence
;AVX: vxorps [[XMM6:%xmm6]], [[XMM6]], [[XMM6]]
;AVX-NEXT: vcvtsi2sdq {{.*}}, [[XMM6]], {{%xmm[0-9]+}}
}
; Make sure we are making a smart choice regarding undef registers in order to
; avoid a cyclic dependence on a write to the same register in a previous
; iteration, especially when we cannot zero out the undef register because it
; is alive.
define i64 @loopclearence(i64* nocapture %x, double* nocapture %y) nounwind {
entry:
%vx = load i64, i64* %x
br label %loop
loop:
%i = phi i64 [ 1, %entry ], [ %inc, %loop ]
%s1 = phi i64 [ %vx, %entry ], [ %s2, %loop ]
%fi = sitofp i64 %i to double
tail call void asm sideeffect "", "~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{dirflag},~{fpsr},~{flags}"()
tail call void asm sideeffect "", "~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{dirflag},~{fpsr},~{flags}"()
tail call void asm sideeffect "", "~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"()
%vy = load double, double* %y
%fipy = fadd double %fi, %vy
%iipy = fptosi double %fipy to i64
%s2 = add i64 %s1, %iipy
%inc = add nsw i64 %i, 1
%exitcond = icmp eq i64 %inc, 156250000
br i1 %exitcond, label %ret, label %loop
ret:
ret i64 %s2
;AVX-LABEL:@loopclearence
;Registers 4-7 are not used and therefore one of them should be chosen
;AVX-NOT: {{%xmm[4-7]}}
;AVX: vcvtsi2sdq {{.*}}, [[XMM4_7:%xmm[4-7]]], {{%xmm[0-9]+}}
;AVX-NOT: [[XMM4_7]]
}

test/CodeGen/X86/copy-propagation.ll

Show All 20 Lines
; Therefore, removing the last copy is wrong. ; Therefore, removing the last copy is wrong.
; ;
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: movl $339752784, %e[[INDIRECT_CALL1:[a-z]+]] ; CHECK: movl $339752784, %e[[INDIRECT_CALL1:[a-z]+]]
; CHECK: callq *%r[[INDIRECT_CALL1]] ; CHECK: callq *%r[[INDIRECT_CALL1]]
; Copy the result in a temporary. ; Copy the result in a temporary.
; Note: Technically the regalloc could have been smarter and this move not required, ; Note: Technically the regalloc could have been smarter and this move not required,
; which would have hidden the bug. ; which would have hidden the bug.
; CHECK-NEXT: vmovapd %xmm0, [[TMP:%xmm[0-9]+]] ; CHECK: vmovapd %xmm0, [[TMP:%xmm[0-9]+]]
; Crush xmm0. ; Crush xmm0.
; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
; CHECK: movl $339772768, %e[[INDIRECT_CALL2:[a-z]+]] ; CHECK: movl $339772768, %e[[INDIRECT_CALL2:[a-z]+]]
; Set TMP in the first argument of the second call. ; Set TMP in the first argument of the second call.
; CHECK-NEXT: vmovapd [[TMP]], %xmm0 ; CHECK-NEXT: vmovapd [[TMP]], %xmm0
; CHECK: callq *%r[[INDIRECT_CALL2]] ; CHECK: callq *%r[[INDIRECT_CALL2]]
; CHECK: retq ; CHECK: retq
define double @foo(i64 %arg) { define double @foo(i64 %arg) {
top: top:
%tmp = call double inttoptr (i64 339752784 to double (double, double)*)(double 1.000000e+00, double 0.000000e+00) %tmp = call double inttoptr (i64 339752784 to double (double, double)*)(double 1.000000e+00, double 0.000000e+00)
tail call void asm sideeffect "", "x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(double %tmp)
%tmp1 = sitofp i64 %arg to double %tmp1 = sitofp i64 %arg to double
call void inttoptr (i64 339772768 to void (double, double)*)(double %tmp, double %tmp1) call void inttoptr (i64 339772768 to void (double, double)*)(double %tmp, double %tmp1)
%tmp3 = fadd double %tmp1, %tmp %tmp3 = fadd double %tmp1, %tmp
ret double %tmp3 ret double %tmp3
} }

test/CodeGen/X86/half.ll

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; CHECK-LIBCALL-NEXT: addss 12(%rsp), %xmm0 ; CHECK-LIBCALL-NEXT: addss 12(%rsp), %xmm0
; CHECK-LIBCALL-NEXT: addq $16, %rsp ; CHECK-LIBCALL-NEXT: addq $16, %rsp
; CHECK-LIBCALL-NEXT: popq %rbx ; CHECK-LIBCALL-NEXT: popq %rbx
; CHECK-LIBCALL-NEXT: retq ; CHECK-LIBCALL-NEXT: retq
; CHECK-F16C-NEXT: movswl (%rsi), %eax ; CHECK-F16C-NEXT: movswl (%rsi), %eax
; CHECK-F16C-NEXT: vmovd %eax, %xmm0 ; CHECK-F16C-NEXT: vmovd %eax, %xmm0
; CHECK-F16C-NEXT: vcvtph2ps %xmm0, %xmm0 ; CHECK-F16C-NEXT: vcvtph2ps %xmm0, %xmm0
; CHECK-F16C-NEXT: vcvtsi2ssl %edi, %xmm0, %xmm1 ; CHECK-F16C-NEXT: vcvtsi2ssl %edi, %xmm1, %xmm1
; CHECK-F16C-NEXT: vcvtps2ph $4, %xmm1, %xmm1 ; CHECK-F16C-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; CHECK-F16C-NEXT: vcvtph2ps %xmm1, %xmm1 ; CHECK-F16C-NEXT: vcvtph2ps %xmm1, %xmm1
; CHECK-F16C-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; CHECK-F16C-NEXT: vaddss %xmm1, %xmm0, %xmm0
; CHECK-F16C-NEXT: retq ; CHECK-F16C-NEXT: retq
define float @test_sitofp_fadd_i32(i32 %a, half* %b) #0 { define float @test_sitofp_fadd_i32(i32 %a, half* %b) #0 {
%tmp0 = load half, half* %b %tmp0 = load half, half* %b
%tmp1 = sitofp i32 %a to half %tmp1 = sitofp i32 %a to half
%tmp2 = fadd half %tmp0, %tmp1 %tmp2 = fadd half %tmp0, %tmp1
%tmp3 = fpext half %tmp2 to float %tmp3 = fpext half %tmp2 to float
ret float %tmp3 ret float %tmp3
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/X86/vec_int_to_fp.ll

Show All 21 Lines
; SSE-NEXT: cvtsi2sdq %rax, %xmm0 ; SSE-NEXT: cvtsi2sdq %rax, %xmm0
; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE-NEXT: movapd %xmm1, %xmm0 ; SSE-NEXT: movapd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: sitofp_2i64_to_2f64: ; AVX-LABEL: sitofp_2i64_to_2f64:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vpextrq $1, %xmm0, %rax ; AVX-NEXT: vpextrq $1, %xmm0, %rax
; AVX-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm1 ; AVX-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1
; AVX-NEXT: vmovq %xmm0, %rax ; AVX-NEXT: vmovq %xmm0, %rax
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0
; AVX-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm0
; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-NEXT: retq ; AVX-NEXT: retq
%cvt = sitofp <2 x i64> %a to <2 x double> %cvt = sitofp <2 x i64> %a to <2 x double>
ret <2 x double> %cvt ret <2 x double> %cvt
} }
define <2 x double> @sitofp_2i32_to_2f64(<4 x i32> %a) { define <2 x double> @sitofp_2i32_to_2f64(<4 x i32> %a) {
; SSE-LABEL: sitofp_2i32_to_2f64: ; SSE-LABEL: sitofp_2i32_to_2f64:
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; SSE-NEXT: movapd %xmm2, %xmm0 ; SSE-NEXT: movapd %xmm2, %xmm0
; SSE-NEXT: movapd %xmm3, %xmm1 ; SSE-NEXT: movapd %xmm3, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: sitofp_4i64_to_4f64: ; AVX1-LABEL: sitofp_4i64_to_4f64:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpextrq $1, %xmm1, %rax ; AVX1-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2
; AVX1-NEXT: vmovq %xmm1, %rax ; AVX1-NEXT: vmovq %xmm1, %rax
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm1 ; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1
; AVX1-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; AVX1-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm0
; AVX1-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; AVX1-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: sitofp_4i64_to_4f64: ; AVX2-LABEL: sitofp_4i64_to_4f64:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpextrq $1, %xmm1, %rax ; AVX2-NEXT: vpextrq $1, %xmm1, %rax
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2
; AVX2-NEXT: vmovq %xmm1, %rax ; AVX2-NEXT: vmovq %xmm1, %rax
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm1 ; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1
; AVX2-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; AVX2-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm0
; AVX2-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; AVX2-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%cvt = sitofp <4 x i64> %a to <4 x double> %cvt = sitofp <4 x i64> %a to <4 x double>
ret <4 x double> %cvt ret <4 x double> %cvt
} }
define <4 x double> @sitofp_4i32_to_4f64(<4 x i32> %a) { define <4 x double> @sitofp_4i32_to_4f64(<4 x i32> %a) {
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; SSE-NEXT: cvtsi2ssq %rax, %xmm0 ; SSE-NEXT: cvtsi2ssq %rax, %xmm0
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE-NEXT: movaps %xmm1, %xmm0 ; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: sitofp_2i64_to_4f32: ; AVX-LABEL: sitofp_2i64_to_4f32:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vpextrq $1, %xmm0, %rax ; AVX-NEXT: vpextrq $1, %xmm0, %rax
; AVX-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX-NEXT: vmovq %xmm0, %rax ; AVX-NEXT: vmovq %xmm0, %rax
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; AVX-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX-NEXT: retq ; AVX-NEXT: retq
%cvt = sitofp <2 x i64> %a to <2 x float> %cvt = sitofp <2 x i64> %a to <2 x float>
%ext = shufflevector <2 x float> %cvt, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %ext = shufflevector <2 x float> %cvt, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x float> %ext ret <4 x float> %ext
} }
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; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE-NEXT: movaps %xmm1, %xmm0 ; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: sitofp_4i64_to_4f32_undef: ; AVX-LABEL: sitofp_4i64_to_4f32_undef:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vpextrq $1, %xmm0, %rax ; AVX-NEXT: vpextrq $1, %xmm0, %rax
; AVX-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX-NEXT: vmovq %xmm0, %rax ; AVX-NEXT: vmovq %xmm0, %rax
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; AVX-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX-NEXT: retq ; AVX-NEXT: retq
%ext = shufflevector <2 x i64> %a, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %ext = shufflevector <2 x i64> %a, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%cvt = sitofp <4 x i64> %ext to <4 x float> %cvt = sitofp <4 x i64> %ext to <4 x float>
ret <4 x float> %cvt ret <4 x float> %cvt
} }
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; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] ; SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; SSE-NEXT: movaps %xmm2, %xmm0 ; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: sitofp_4i64_to_4f32: ; AVX1-LABEL: sitofp_4i64_to_4f32:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: sitofp_4i64_to_4f32: ; AVX2-LABEL: sitofp_4i64_to_4f32:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%cvt = sitofp <4 x i64> %a to <4 x float> %cvt = sitofp <4 x i64> %a to <4 x float>
ret <4 x float> %cvt ret <4 x float> %cvt
} }
define <8 x float> @sitofp_8i32_to_8f32(<8 x i32> %a) { define <8 x float> @sitofp_8i32_to_8f32(<8 x i32> %a) {
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; AVX-LABEL: uitofp_2i64_to_4f32: ; AVX-LABEL: uitofp_2i64_to_4f32:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vpextrq $1, %xmm0, %rax ; AVX-NEXT: vpextrq $1, %xmm0, %rax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: andl $1, %ecx ; AVX-NEXT: andl $1, %ecx
; AVX-NEXT: testq %rax, %rax ; AVX-NEXT: testq %rax, %rax
; AVX-NEXT: js .LBB38_1 ; AVX-NEXT: js .LBB38_1
; AVX-NEXT: # BB#2: ; AVX-NEXT: # BB#2:
; AVX-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX-NEXT: jmp .LBB38_3 ; AVX-NEXT: jmp .LBB38_3
; AVX-NEXT: .LBB38_1: ; AVX-NEXT: .LBB38_1:
; AVX-NEXT: shrq %rax ; AVX-NEXT: shrq %rax
; AVX-NEXT: orq %rax, %rcx ; AVX-NEXT: orq %rax, %rcx
; AVX-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm1 ; AVX-NEXT: vcvtsi2ssq %rcx, %xmm1, %xmm1
; AVX-NEXT: vaddss %xmm1, %xmm1, %xmm1 ; AVX-NEXT: vaddss %xmm1, %xmm1, %xmm1
; AVX-NEXT: .LBB38_3: ; AVX-NEXT: .LBB38_3:
; AVX-NEXT: vmovq %xmm0, %rax ; AVX-NEXT: vmovq %xmm0, %rax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: andl $1, %ecx ; AVX-NEXT: andl $1, %ecx
; AVX-NEXT: testq %rax, %rax ; AVX-NEXT: testq %rax, %rax
; AVX-NEXT: js .LBB38_4 ; AVX-NEXT: js .LBB38_4
; AVX-NEXT: # BB#5: ; AVX-NEXT: # BB#5:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; AVX-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
; AVX-NEXT: jmp .LBB38_6 ; AVX-NEXT: jmp .LBB38_6
; AVX-NEXT: .LBB38_4: ; AVX-NEXT: .LBB38_4:
; AVX-NEXT: shrq %rax ; AVX-NEXT: shrq %rax
; AVX-NEXT: orq %rax, %rcx ; AVX-NEXT: orq %rax, %rcx
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vcvtsi2ssq %rcx, %xmm2, %xmm0
; AVX-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm0
; AVX-NEXT: vaddss %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm0, %xmm0, %xmm0
; AVX-NEXT: .LBB38_6: ; AVX-NEXT: .LBB38_6:
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-NEXT: testq %rax, %rax ; AVX-NEXT: testq %rax, %rax
; AVX-NEXT: js .LBB38_8 ; AVX-NEXT: js .LBB38_8
; AVX-NEXT: # BB#7: ; AVX-NEXT: # BB#7:
; AVX-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1
; AVX-NEXT: .LBB38_8: ; AVX-NEXT: .LBB38_8:
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX-NEXT: retq ; AVX-NEXT: retq
%cvt = uitofp <2 x i64> %a to <2 x float> %cvt = uitofp <2 x i64> %a to <2 x float>
%ext = shufflevector <2 x float> %cvt, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %ext = shufflevector <2 x float> %cvt, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x float> %ext ret <4 x float> %ext
} }
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; AVX-LABEL: uitofp_4i64_to_4f32_undef: ; AVX-LABEL: uitofp_4i64_to_4f32_undef:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vpextrq $1, %xmm0, %rax ; AVX-NEXT: vpextrq $1, %xmm0, %rax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: andl $1, %ecx ; AVX-NEXT: andl $1, %ecx
; AVX-NEXT: testq %rax, %rax ; AVX-NEXT: testq %rax, %rax
; AVX-NEXT: js .LBB39_1 ; AVX-NEXT: js .LBB39_1
; AVX-NEXT: # BB#2: ; AVX-NEXT: # BB#2:
; AVX-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX-NEXT: jmp .LBB39_3 ; AVX-NEXT: jmp .LBB39_3
; AVX-NEXT: .LBB39_1: ; AVX-NEXT: .LBB39_1:
; AVX-NEXT: shrq %rax ; AVX-NEXT: shrq %rax
; AVX-NEXT: orq %rax, %rcx ; AVX-NEXT: orq %rax, %rcx
; AVX-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm1 ; AVX-NEXT: vcvtsi2ssq %rcx, %xmm1, %xmm1
; AVX-NEXT: vaddss %xmm1, %xmm1, %xmm1 ; AVX-NEXT: vaddss %xmm1, %xmm1, %xmm1
; AVX-NEXT: .LBB39_3: ; AVX-NEXT: .LBB39_3:
; AVX-NEXT: vmovq %xmm0, %rax ; AVX-NEXT: vmovq %xmm0, %rax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: andl $1, %ecx ; AVX-NEXT: andl $1, %ecx
; AVX-NEXT: testq %rax, %rax ; AVX-NEXT: testq %rax, %rax
; AVX-NEXT: js .LBB39_4 ; AVX-NEXT: js .LBB39_4
; AVX-NEXT: # BB#5: ; AVX-NEXT: # BB#5:
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
; AVX-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
; AVX-NEXT: jmp .LBB39_6 ; AVX-NEXT: jmp .LBB39_6
; AVX-NEXT: .LBB39_4: ; AVX-NEXT: .LBB39_4:
; AVX-NEXT: shrq %rax ; AVX-NEXT: shrq %rax
; AVX-NEXT: orq %rax, %rcx ; AVX-NEXT: orq %rax, %rcx
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vcvtsi2ssq %rcx, %xmm2, %xmm0
; AVX-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm0
; AVX-NEXT: vaddss %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm0, %xmm0, %xmm0
; AVX-NEXT: .LBB39_6: ; AVX-NEXT: .LBB39_6:
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-NEXT: testq %rax, %rax ; AVX-NEXT: testq %rax, %rax
; AVX-NEXT: js .LBB39_8 ; AVX-NEXT: js .LBB39_8
; AVX-NEXT: # BB#7: ; AVX-NEXT: # BB#7:
; AVX-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1
; AVX-NEXT: .LBB39_8: ; AVX-NEXT: .LBB39_8:
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX-NEXT: retq ; AVX-NEXT: retq
%ext = shufflevector <2 x i64> %a, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %ext = shufflevector <2 x i64> %a, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%cvt = uitofp <4 x i64> %ext to <4 x float> %cvt = uitofp <4 x i64> %ext to <4 x float>
ret <4 x float> %cvt ret <4 x float> %cvt
} }
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; AVX1-LABEL: uitofp_4i64_to_4f32: ; AVX1-LABEL: uitofp_4i64_to_4f32:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB45_1 ; AVX1-NEXT: js .LBB45_1
; AVX1-NEXT: # BB#2: ; AVX1-NEXT: # BB#2:
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX1-NEXT: jmp .LBB45_3 ; AVX1-NEXT: jmp .LBB45_3
; AVX1-NEXT: .LBB45_1: ; AVX1-NEXT: .LBB45_1:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm1 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm1, %xmm1
; AVX1-NEXT: vaddss %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vaddss %xmm1, %xmm1, %xmm1
; AVX1-NEXT: .LBB45_3: ; AVX1-NEXT: .LBB45_3:
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB45_4 ; AVX1-NEXT: js .LBB45_4
; AVX1-NEXT: # BB#5: ; AVX1-NEXT: # BB#5:
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX1-NEXT: jmp .LBB45_6 ; AVX1-NEXT: jmp .LBB45_6
; AVX1-NEXT: .LBB45_4: ; AVX1-NEXT: .LBB45_4:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm2, %xmm2
; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2
; AVX1-NEXT: .LBB45_6: ; AVX1-NEXT: .LBB45_6:
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB45_7 ; AVX1-NEXT: js .LBB45_7
; AVX1-NEXT: # BB#8: ; AVX1-NEXT: # BB#8:
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
; AVX1-NEXT: jmp .LBB45_9 ; AVX1-NEXT: jmp .LBB45_9
; AVX1-NEXT: .LBB45_7: ; AVX1-NEXT: .LBB45_7:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm3, %xmm2
; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2
; AVX1-NEXT: .LBB45_9: ; AVX1-NEXT: .LBB45_9:
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB45_10 ; AVX1-NEXT: js .LBB45_10
; AVX1-NEXT: # BB#11: ; AVX1-NEXT: # BB#11:
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; AVX1-NEXT: .LBB45_10: ; AVX1-NEXT: .LBB45_10:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm3, %xmm0
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm0
; AVX1-NEXT: vaddss %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vaddss %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: uitofp_4i64_to_4f32: ; AVX2-LABEL: uitofp_4i64_to_4f32:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB45_1 ; AVX2-NEXT: js .LBB45_1
; AVX2-NEXT: # BB#2: ; AVX2-NEXT: # BB#2:
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX2-NEXT: jmp .LBB45_3 ; AVX2-NEXT: jmp .LBB45_3
; AVX2-NEXT: .LBB45_1: ; AVX2-NEXT: .LBB45_1:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm1 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm1, %xmm1
; AVX2-NEXT: vaddss %xmm1, %xmm1, %xmm1 ; AVX2-NEXT: vaddss %xmm1, %xmm1, %xmm1
; AVX2-NEXT: .LBB45_3: ; AVX2-NEXT: .LBB45_3:
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB45_4 ; AVX2-NEXT: js .LBB45_4
; AVX2-NEXT: # BB#5: ; AVX2-NEXT: # BB#5:
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX2-NEXT: jmp .LBB45_6 ; AVX2-NEXT: jmp .LBB45_6
; AVX2-NEXT: .LBB45_4: ; AVX2-NEXT: .LBB45_4:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm2, %xmm2
; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2 ; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2
; AVX2-NEXT: .LBB45_6: ; AVX2-NEXT: .LBB45_6:
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB45_7 ; AVX2-NEXT: js .LBB45_7
; AVX2-NEXT: # BB#8: ; AVX2-NEXT: # BB#8:
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
; AVX2-NEXT: jmp .LBB45_9 ; AVX2-NEXT: jmp .LBB45_9
; AVX2-NEXT: .LBB45_7: ; AVX2-NEXT: .LBB45_7:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm3, %xmm2
; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2 ; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2
; AVX2-NEXT: .LBB45_9: ; AVX2-NEXT: .LBB45_9:
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB45_10 ; AVX2-NEXT: js .LBB45_10
; AVX2-NEXT: # BB#11: ; AVX2-NEXT: # BB#11:
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; AVX2-NEXT: .LBB45_10: ; AVX2-NEXT: .LBB45_10:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm3, %xmm0
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm0
; AVX2-NEXT: vaddss %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vaddss %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%cvt = uitofp <4 x i64> %a to <4 x float> %cvt = uitofp <4 x i64> %a to <4 x float>
ret <4 x float> %cvt ret <4 x float> %cvt
} }
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; SSE-NEXT: cvtsi2sdq %rax, %xmm1 ; SSE-NEXT: cvtsi2sdq %rax, %xmm1
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: sitofp_load_2i64_to_2f64: ; AVX-LABEL: sitofp_load_2i64_to_2f64:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa (%rdi), %xmm0 ; AVX-NEXT: vmovdqa (%rdi), %xmm0
; AVX-NEXT: vpextrq $1, %xmm0, %rax ; AVX-NEXT: vpextrq $1, %xmm0, %rax
; AVX-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm1 ; AVX-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1
; AVX-NEXT: vmovq %xmm0, %rax ; AVX-NEXT: vmovq %xmm0, %rax
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0
; AVX-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm0
; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-NEXT: retq ; AVX-NEXT: retq
%ld = load <2 x i64>, <2 x i64> *%a %ld = load <2 x i64>, <2 x i64> *%a
%cvt = sitofp <2 x i64> %ld to <2 x double> %cvt = sitofp <2 x i64> %ld to <2 x double>
ret <2 x double> %cvt ret <2 x double> %cvt
} }
define <2 x double> @sitofp_load_2i32_to_2f64(<2 x i32> *%a) { define <2 x double> @sitofp_load_2i32_to_2f64(<2 x i32> *%a) {
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; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: sitofp_load_4i64_to_4f64: ; AVX1-LABEL: sitofp_load_4i64_to_4f64:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vmovaps (%rdi), %ymm0 ; AVX1-NEXT: vmovaps (%rdi), %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpextrq $1, %xmm1, %rax ; AVX1-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2
; AVX1-NEXT: vmovq %xmm1, %rax ; AVX1-NEXT: vmovq %xmm1, %rax
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm1 ; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1
; AVX1-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; AVX1-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0
; AVX1-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm0
; AVX1-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; AVX1-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: sitofp_load_4i64_to_4f64: ; AVX2-LABEL: sitofp_load_4i64_to_4f64:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0 ; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vpextrq $1, %xmm1, %rax ; AVX2-NEXT: vpextrq $1, %xmm1, %rax
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2
; AVX2-NEXT: vmovq %xmm1, %rax ; AVX2-NEXT: vmovq %xmm1, %rax
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm1 ; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1
; AVX2-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; AVX2-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0
; AVX2-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm0
; AVX2-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; AVX2-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%ld = load <4 x i64>, <4 x i64> *%a %ld = load <4 x i64>, <4 x i64> *%a
%cvt = sitofp <4 x i64> %ld to <4 x double> %cvt = sitofp <4 x i64> %ld to <4 x double>
ret <4 x double> %cvt ret <4 x double> %cvt
} }
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; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: sitofp_load_4i64_to_4f32: ; AVX1-LABEL: sitofp_load_4i64_to_4f32:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vmovdqa (%rdi), %ymm0 ; AVX1-NEXT: vmovdqa (%rdi), %ymm0
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: sitofp_load_4i64_to_4f32: ; AVX2-LABEL: sitofp_load_4i64_to_4f32:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0 ; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%ld = load <4 x i64>, <4 x i64> *%a %ld = load <4 x i64>, <4 x i64> *%a
%cvt = sitofp <4 x i64> %ld to <4 x float> %cvt = sitofp <4 x i64> %ld to <4 x float>
ret <4 x float> %cvt ret <4 x float> %cvt
} }
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; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] ; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: sitofp_load_8i64_to_8f32: ; AVX1-LABEL: sitofp_load_8i64_to_8f32:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vmovdqa (%rdi), %ymm0 ; AVX1-NEXT: vmovdqa (%rdi), %ymm0
; AVX1-NEXT: vmovdqa 32(%rdi), %ymm1 ; AVX1-NEXT: vmovdqa 32(%rdi), %ymm1
; AVX1-NEXT: vpextrq $1, %xmm1, %rax ; AVX1-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX1-NEXT: vmovq %xmm1, %rax ; AVX1-NEXT: vmovq %xmm1, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm3 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm3
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vmovq %xmm1, %rax ; AVX1-NEXT: vmovq %xmm1, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm3 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX1-NEXT: vpextrq $1, %xmm1, %rax ; AVX1-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm1
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm2
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm3 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm3 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm0
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: sitofp_load_8i64_to_8f32: ; AVX2-LABEL: sitofp_load_8i64_to_8f32:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0 ; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vmovdqa 32(%rdi), %ymm1 ; AVX2-NEXT: vmovdqa 32(%rdi), %ymm1
; AVX2-NEXT: vpextrq $1, %xmm1, %rax ; AVX2-NEXT: vpextrq $1, %xmm1, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX2-NEXT: vmovq %xmm1, %rax ; AVX2-NEXT: vmovq %xmm1, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm3 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm3
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1
; AVX2-NEXT: vmovq %xmm1, %rax ; AVX2-NEXT: vmovq %xmm1, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm3 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX2-NEXT: vpextrq $1, %xmm1, %rax ; AVX2-NEXT: vpextrq $1, %xmm1, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm1
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm2
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm3 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm3 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm3
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm0
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%ld = load <8 x i64>, <8 x i64> *%a %ld = load <8 x i64>, <8 x i64> *%a
%cvt = sitofp <8 x i64> %ld to <8 x float> %cvt = sitofp <8 x i64> %ld to <8 x float>
ret <8 x float> %cvt ret <8 x float> %cvt
} }
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; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vmovdqa (%rdi), %ymm0 ; AVX1-NEXT: vmovdqa (%rdi), %ymm0
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB74_1 ; AVX1-NEXT: js .LBB74_1
; AVX1-NEXT: # BB#2: ; AVX1-NEXT: # BB#2:
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX1-NEXT: jmp .LBB74_3 ; AVX1-NEXT: jmp .LBB74_3
; AVX1-NEXT: .LBB74_1: ; AVX1-NEXT: .LBB74_1:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm1 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm1, %xmm1
; AVX1-NEXT: vaddss %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vaddss %xmm1, %xmm1, %xmm1
; AVX1-NEXT: .LBB74_3: ; AVX1-NEXT: .LBB74_3:
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB74_4 ; AVX1-NEXT: js .LBB74_4
; AVX1-NEXT: # BB#5: ; AVX1-NEXT: # BB#5:
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX1-NEXT: jmp .LBB74_6 ; AVX1-NEXT: jmp .LBB74_6
; AVX1-NEXT: .LBB74_4: ; AVX1-NEXT: .LBB74_4:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm2, %xmm2
; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2
; AVX1-NEXT: .LBB74_6: ; AVX1-NEXT: .LBB74_6:
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB74_7 ; AVX1-NEXT: js .LBB74_7
; AVX1-NEXT: # BB#8: ; AVX1-NEXT: # BB#8:
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
; AVX1-NEXT: jmp .LBB74_9 ; AVX1-NEXT: jmp .LBB74_9
; AVX1-NEXT: .LBB74_7: ; AVX1-NEXT: .LBB74_7:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm3, %xmm2
; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2
; AVX1-NEXT: .LBB74_9: ; AVX1-NEXT: .LBB74_9:
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB74_10 ; AVX1-NEXT: js .LBB74_10
; AVX1-NEXT: # BB#11: ; AVX1-NEXT: # BB#11:
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; AVX1-NEXT: .LBB74_10: ; AVX1-NEXT: .LBB74_10:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm3, %xmm0
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm0
; AVX1-NEXT: vaddss %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vaddss %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: uitofp_load_4i64_to_4f32: ; AVX2-LABEL: uitofp_load_4i64_to_4f32:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0 ; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB74_1 ; AVX2-NEXT: js .LBB74_1
; AVX2-NEXT: # BB#2: ; AVX2-NEXT: # BB#2:
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX2-NEXT: jmp .LBB74_3 ; AVX2-NEXT: jmp .LBB74_3
; AVX2-NEXT: .LBB74_1: ; AVX2-NEXT: .LBB74_1:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm1 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm1, %xmm1
; AVX2-NEXT: vaddss %xmm1, %xmm1, %xmm1 ; AVX2-NEXT: vaddss %xmm1, %xmm1, %xmm1
; AVX2-NEXT: .LBB74_3: ; AVX2-NEXT: .LBB74_3:
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB74_4 ; AVX2-NEXT: js .LBB74_4
; AVX2-NEXT: # BB#5: ; AVX2-NEXT: # BB#5:
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2
; AVX2-NEXT: jmp .LBB74_6 ; AVX2-NEXT: jmp .LBB74_6
; AVX2-NEXT: .LBB74_4: ; AVX2-NEXT: .LBB74_4:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm2, %xmm2
; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2 ; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2
; AVX2-NEXT: .LBB74_6: ; AVX2-NEXT: .LBB74_6:
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB74_7 ; AVX2-NEXT: js .LBB74_7
; AVX2-NEXT: # BB#8: ; AVX2-NEXT: # BB#8:
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2
; AVX2-NEXT: jmp .LBB74_9 ; AVX2-NEXT: jmp .LBB74_9
; AVX2-NEXT: .LBB74_7: ; AVX2-NEXT: .LBB74_7:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm3, %xmm2
; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2 ; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2
; AVX2-NEXT: .LBB74_9: ; AVX2-NEXT: .LBB74_9:
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB74_10 ; AVX2-NEXT: js .LBB74_10
; AVX2-NEXT: # BB#11: ; AVX2-NEXT: # BB#11:
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm0
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; AVX2-NEXT: .LBB74_10: ; AVX2-NEXT: .LBB74_10:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm3, %xmm0
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm0
; AVX2-NEXT: vaddss %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vaddss %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%ld = load <4 x i64>, <4 x i64> *%a %ld = load <4 x i64>, <4 x i64> *%a
%cvt = uitofp <4 x i64> %ld to <4 x float> %cvt = uitofp <4 x i64> %ld to <4 x float>
ret <4 x float> %cvt ret <4 x float> %cvt
} }
▲ Show 20 Lines • Show All 221 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vmovdqa (%rdi), %ymm0 ; AVX1-NEXT: vmovdqa (%rdi), %ymm0
; AVX1-NEXT: vmovdqa 32(%rdi), %ymm2 ; AVX1-NEXT: vmovdqa 32(%rdi), %ymm2
; AVX1-NEXT: vpextrq $1, %xmm2, %rax ; AVX1-NEXT: vpextrq $1, %xmm2, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB78_1 ; AVX1-NEXT: js .LBB78_1
; AVX1-NEXT: # BB#2: ; AVX1-NEXT: # BB#2:
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX1-NEXT: jmp .LBB78_3 ; AVX1-NEXT: jmp .LBB78_3
; AVX1-NEXT: .LBB78_1: ; AVX1-NEXT: .LBB78_1:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm1 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm1, %xmm1
; AVX1-NEXT: vaddss %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vaddss %xmm1, %xmm1, %xmm1
; AVX1-NEXT: .LBB78_3: ; AVX1-NEXT: .LBB78_3:
; AVX1-NEXT: vmovq %xmm2, %rax ; AVX1-NEXT: vmovq %xmm2, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB78_4 ; AVX1-NEXT: js .LBB78_4
; AVX1-NEXT: # BB#5: ; AVX1-NEXT: # BB#5:
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm3 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm3
; AVX1-NEXT: jmp .LBB78_6 ; AVX1-NEXT: jmp .LBB78_6
; AVX1-NEXT: .LBB78_4: ; AVX1-NEXT: .LBB78_4:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm3 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm3, %xmm3
; AVX1-NEXT: vaddss %xmm3, %xmm3, %xmm3 ; AVX1-NEXT: vaddss %xmm3, %xmm3, %xmm3
; AVX1-NEXT: .LBB78_6: ; AVX1-NEXT: .LBB78_6:
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
; AVX1-NEXT: vmovq %xmm2, %rax ; AVX1-NEXT: vmovq %xmm2, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB78_7 ; AVX1-NEXT: js .LBB78_7
; AVX1-NEXT: # BB#8: ; AVX1-NEXT: # BB#8:
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm4 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm4
; AVX1-NEXT: jmp .LBB78_9 ; AVX1-NEXT: jmp .LBB78_9
; AVX1-NEXT: .LBB78_7: ; AVX1-NEXT: .LBB78_7:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm4 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm4, %xmm4
; AVX1-NEXT: vaddss %xmm4, %xmm4, %xmm4 ; AVX1-NEXT: vaddss %xmm4, %xmm4, %xmm4
; AVX1-NEXT: .LBB78_9: ; AVX1-NEXT: .LBB78_9:
; AVX1-NEXT: vpextrq $1, %xmm2, %rax ; AVX1-NEXT: vpextrq $1, %xmm2, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB78_10 ; AVX1-NEXT: js .LBB78_10
; AVX1-NEXT: # BB#11: ; AVX1-NEXT: # BB#11:
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm2
; AVX1-NEXT: jmp .LBB78_12 ; AVX1-NEXT: jmp .LBB78_12
; AVX1-NEXT: .LBB78_10: ; AVX1-NEXT: .LBB78_10:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm5, %xmm2
; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2
; AVX1-NEXT: .LBB78_12: ; AVX1-NEXT: .LBB78_12:
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB78_13 ; AVX1-NEXT: js .LBB78_13
; AVX1-NEXT: # BB#14: ; AVX1-NEXT: # BB#14:
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm5 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm5
; AVX1-NEXT: jmp .LBB78_15 ; AVX1-NEXT: jmp .LBB78_15
; AVX1-NEXT: .LBB78_13: ; AVX1-NEXT: .LBB78_13:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm5 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm5, %xmm5
; AVX1-NEXT: vaddss %xmm5, %xmm5, %xmm5 ; AVX1-NEXT: vaddss %xmm5, %xmm5, %xmm5
; AVX1-NEXT: .LBB78_15: ; AVX1-NEXT: .LBB78_15:
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[2,3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[2,3]
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB78_16 ; AVX1-NEXT: js .LBB78_16
; AVX1-NEXT: # BB#17: ; AVX1-NEXT: # BB#17:
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm3 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm3
; AVX1-NEXT: jmp .LBB78_18 ; AVX1-NEXT: jmp .LBB78_18
; AVX1-NEXT: .LBB78_16: ; AVX1-NEXT: .LBB78_16:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm3 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm6, %xmm3
; AVX1-NEXT: vaddss %xmm3, %xmm3, %xmm3 ; AVX1-NEXT: vaddss %xmm3, %xmm3, %xmm3
; AVX1-NEXT: .LBB78_18: ; AVX1-NEXT: .LBB78_18:
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm4[0],xmm1[3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm4[0],xmm1[3]
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[2,3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
; AVX1-NEXT: vmovq %xmm4, %rax ; AVX1-NEXT: vmovq %xmm4, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB78_19 ; AVX1-NEXT: js .LBB78_19
; AVX1-NEXT: # BB#20: ; AVX1-NEXT: # BB#20:
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm5
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm5
; AVX1-NEXT: jmp .LBB78_21 ; AVX1-NEXT: jmp .LBB78_21
; AVX1-NEXT: .LBB78_19: ; AVX1-NEXT: .LBB78_19:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm6, %xmm0
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm0
; AVX1-NEXT: vaddss %xmm0, %xmm0, %xmm5 ; AVX1-NEXT: vaddss %xmm0, %xmm0, %xmm5
; AVX1-NEXT: .LBB78_21: ; AVX1-NEXT: .LBB78_21:
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm2[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm2[0]
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1],xmm5[0],xmm3[3] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1],xmm5[0],xmm3[3]
; AVX1-NEXT: vpextrq $1, %xmm4, %rax ; AVX1-NEXT: vpextrq $1, %xmm4, %rax
; AVX1-NEXT: movl %eax, %ecx ; AVX1-NEXT: movl %eax, %ecx
; AVX1-NEXT: andl $1, %ecx ; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: testq %rax, %rax ; AVX1-NEXT: testq %rax, %rax
; AVX1-NEXT: js .LBB78_22 ; AVX1-NEXT: js .LBB78_22
; AVX1-NEXT: # BB#23: ; AVX1-NEXT: # BB#23:
; AVX1-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm2
; AVX1-NEXT: jmp .LBB78_24 ; AVX1-NEXT: jmp .LBB78_24
; AVX1-NEXT: .LBB78_22: ; AVX1-NEXT: .LBB78_22:
; AVX1-NEXT: shrq %rax ; AVX1-NEXT: shrq %rax
; AVX1-NEXT: orq %rax, %rcx ; AVX1-NEXT: orq %rax, %rcx
; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm2 ; AVX1-NEXT: vcvtsi2ssq %rcx, %xmm6, %xmm2
; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2
; AVX1-NEXT: .LBB78_24: ; AVX1-NEXT: .LBB78_24:
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: uitofp_load_8i64_to_8f32: ; AVX2-LABEL: uitofp_load_8i64_to_8f32:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0 ; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vmovdqa 32(%rdi), %ymm2 ; AVX2-NEXT: vmovdqa 32(%rdi), %ymm2
; AVX2-NEXT: vpextrq $1, %xmm2, %rax ; AVX2-NEXT: vpextrq $1, %xmm2, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB78_1 ; AVX2-NEXT: js .LBB78_1
; AVX2-NEXT: # BB#2: ; AVX2-NEXT: # BB#2:
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm1 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
; AVX2-NEXT: jmp .LBB78_3 ; AVX2-NEXT: jmp .LBB78_3
; AVX2-NEXT: .LBB78_1: ; AVX2-NEXT: .LBB78_1:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm1 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm1, %xmm1
; AVX2-NEXT: vaddss %xmm1, %xmm1, %xmm1 ; AVX2-NEXT: vaddss %xmm1, %xmm1, %xmm1
; AVX2-NEXT: .LBB78_3: ; AVX2-NEXT: .LBB78_3:
; AVX2-NEXT: vmovq %xmm2, %rax ; AVX2-NEXT: vmovq %xmm2, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB78_4 ; AVX2-NEXT: js .LBB78_4
; AVX2-NEXT: # BB#5: ; AVX2-NEXT: # BB#5:
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm3 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm3
; AVX2-NEXT: jmp .LBB78_6 ; AVX2-NEXT: jmp .LBB78_6
; AVX2-NEXT: .LBB78_4: ; AVX2-NEXT: .LBB78_4:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm3 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm3, %xmm3
; AVX2-NEXT: vaddss %xmm3, %xmm3, %xmm3 ; AVX2-NEXT: vaddss %xmm3, %xmm3, %xmm3
; AVX2-NEXT: .LBB78_6: ; AVX2-NEXT: .LBB78_6:
; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm2 ; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm2
; AVX2-NEXT: vmovq %xmm2, %rax ; AVX2-NEXT: vmovq %xmm2, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB78_7 ; AVX2-NEXT: js .LBB78_7
; AVX2-NEXT: # BB#8: ; AVX2-NEXT: # BB#8:
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm4 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm4
; AVX2-NEXT: jmp .LBB78_9 ; AVX2-NEXT: jmp .LBB78_9
; AVX2-NEXT: .LBB78_7: ; AVX2-NEXT: .LBB78_7:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm4 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm4, %xmm4
; AVX2-NEXT: vaddss %xmm4, %xmm4, %xmm4 ; AVX2-NEXT: vaddss %xmm4, %xmm4, %xmm4
; AVX2-NEXT: .LBB78_9: ; AVX2-NEXT: .LBB78_9:
; AVX2-NEXT: vpextrq $1, %xmm2, %rax ; AVX2-NEXT: vpextrq $1, %xmm2, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB78_10 ; AVX2-NEXT: js .LBB78_10
; AVX2-NEXT: # BB#11: ; AVX2-NEXT: # BB#11:
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm2
; AVX2-NEXT: jmp .LBB78_12 ; AVX2-NEXT: jmp .LBB78_12
; AVX2-NEXT: .LBB78_10: ; AVX2-NEXT: .LBB78_10:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm5, %xmm2
; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2 ; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2
; AVX2-NEXT: .LBB78_12: ; AVX2-NEXT: .LBB78_12:
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB78_13 ; AVX2-NEXT: js .LBB78_13
; AVX2-NEXT: # BB#14: ; AVX2-NEXT: # BB#14:
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm5 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm5
; AVX2-NEXT: jmp .LBB78_15 ; AVX2-NEXT: jmp .LBB78_15
; AVX2-NEXT: .LBB78_13: ; AVX2-NEXT: .LBB78_13:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm5 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm5, %xmm5
; AVX2-NEXT: vaddss %xmm5, %xmm5, %xmm5 ; AVX2-NEXT: vaddss %xmm5, %xmm5, %xmm5
; AVX2-NEXT: .LBB78_15: ; AVX2-NEXT: .LBB78_15:
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[2,3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[2,3]
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB78_16 ; AVX2-NEXT: js .LBB78_16
; AVX2-NEXT: # BB#17: ; AVX2-NEXT: # BB#17:
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm3 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm3
; AVX2-NEXT: jmp .LBB78_18 ; AVX2-NEXT: jmp .LBB78_18
; AVX2-NEXT: .LBB78_16: ; AVX2-NEXT: .LBB78_16:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm3 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm6, %xmm3
; AVX2-NEXT: vaddss %xmm3, %xmm3, %xmm3 ; AVX2-NEXT: vaddss %xmm3, %xmm3, %xmm3
; AVX2-NEXT: .LBB78_18: ; AVX2-NEXT: .LBB78_18:
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm4[0],xmm1[3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm4[0],xmm1[3]
; AVX2-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[2,3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[2,3]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm4 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm4
; AVX2-NEXT: vmovq %xmm4, %rax ; AVX2-NEXT: vmovq %xmm4, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB78_19 ; AVX2-NEXT: js .LBB78_19
; AVX2-NEXT: # BB#20: ; AVX2-NEXT: # BB#20:
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm5
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm5
; AVX2-NEXT: jmp .LBB78_21 ; AVX2-NEXT: jmp .LBB78_21
; AVX2-NEXT: .LBB78_19: ; AVX2-NEXT: .LBB78_19:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm6, %xmm0
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm0
; AVX2-NEXT: vaddss %xmm0, %xmm0, %xmm5 ; AVX2-NEXT: vaddss %xmm0, %xmm0, %xmm5
; AVX2-NEXT: .LBB78_21: ; AVX2-NEXT: .LBB78_21:
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm2[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm2[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1],xmm5[0],xmm3[3] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1],xmm5[0],xmm3[3]
; AVX2-NEXT: vpextrq $1, %xmm4, %rax ; AVX2-NEXT: vpextrq $1, %xmm4, %rax
; AVX2-NEXT: movl %eax, %ecx ; AVX2-NEXT: movl %eax, %ecx
; AVX2-NEXT: andl $1, %ecx ; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: testq %rax, %rax ; AVX2-NEXT: testq %rax, %rax
; AVX2-NEXT: js .LBB78_22 ; AVX2-NEXT: js .LBB78_22
; AVX2-NEXT: # BB#23: ; AVX2-NEXT: # BB#23:
; AVX2-NEXT: vcvtsi2ssq %rax, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm2
; AVX2-NEXT: jmp .LBB78_24 ; AVX2-NEXT: jmp .LBB78_24
; AVX2-NEXT: .LBB78_22: ; AVX2-NEXT: .LBB78_22:
; AVX2-NEXT: shrq %rax ; AVX2-NEXT: shrq %rax
; AVX2-NEXT: orq %rax, %rcx ; AVX2-NEXT: orq %rax, %rcx
; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm0, %xmm2 ; AVX2-NEXT: vcvtsi2ssq %rcx, %xmm6, %xmm2
; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2 ; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2
; AVX2-NEXT: .LBB78_24: ; AVX2-NEXT: .LBB78_24:
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; AVX2-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX2-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%ld = load <8 x i64>, <8 x i64> *%a %ld = load <8 x i64>, <8 x i64> *%a
%cvt = uitofp <8 x i64> %ld to <8 x float> %cvt = uitofp <8 x i64> %ld to <8 x float>
ret <8 x float> %cvt ret <8 x float> %cvt
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