AMDGPU: Fix trying to skip from a block with no successors

[arsenm]

Summary

Found while reducing bug 28550

[• tstellarAMD]

LGTM.

[arsenm]

r275509

lib/Target/AMDGPU/SILowerControlFlow.cpp

case TargetOpcode::DBG_VALUE:
     return true;
   default:
     return false;
   }
 }
 
 bool SILowerControlFlow::shouldSkip(MachineBasicBlock *From,
                                     MachineBasicBlock *To) {
+  if (From->succ_empty())
+    return false;
 
   unsigned NumInstr = 0;
   MachineFunction *MF = From->getParent();
 
   for (MachineFunction::iterator MBBI(From), ToI(To), End = MF->end();
        MBBI != End && MBBI != ToI; ++MBBI) {
     MachineBasicBlock &MBB = *MBBI;
 
bool SILowerControlFlow::skipIfDead(MachineInstr &MI, MachineBasicBlock &NextBB) {
   MachineBasicBlock &MBB = *MI.getParent();
   MachineFunction *MF = MBB.getParent();
 
   if (MF->getFunction()->getCallingConv() != CallingConv::AMDGPU_PS ||
       !shouldSkip(&MBB, &MBB.getParent()->back()))
     return false;
 
   MachineBasicBlock *SkipBB = insertSkipBlock(MBB, MI.getIterator());
-  SkipBB->addSuccessor(&NextBB);
+  MBB.addSuccessor(SkipBB);
 
   const DebugLoc &DL = MI.getDebugLoc();
 
   // If the exec mask is non-zero, skip the next two instructions
   BuildMI(&MBB, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
     .addMBB(&NextBB);
 
   MachineBasicBlock::iterator Insert = SkipBB->begin();
MachineBasicBlock *SILowerControlFlow::insertSkipBlock(
   MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const {
   MachineFunction *MF = MBB.getParent();
 
   MachineBasicBlock *SkipBB = MF->CreateMachineBasicBlock();
   MachineFunction::iterator MBBI(MBB);
   ++MBBI;
 
   MF->insert(MBBI, SkipBB);
-  MBB.addSuccessor(SkipBB);
 
   return SkipBB;
 }
 
 std::pair<MachineBasicBlock *, MachineBasicBlock *>
 SILowerControlFlow::splitBlock(MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator I) {
   MachineFunction *MF = MBB.getParent();

test/CodeGen/AMDGPU/skip-if-dead.ll

 bb10:
   store volatile i32 9, i32 addrspace(1)* undef
   br label %end
 
 end:
   ret void
 }
 
+; CHECK-LABEL: {{^}}no_skip_no_successors:
+; CHECK: v_cmp_nle_f32
+; CHECK: s_and_b64 vcc, exec,
+; CHECK: s_cbranch_vccz [[SKIPKILL:BB[0-9]+_[0-9]+]]
+
+; CHECK: ; BB#3: ; %bb6
+; CHECK: s_mov_b64 exec, 0
+
+; CHECK: [[SKIPKILL]]:
+; CHECK: v_cmp_nge_f32
+; CHECK: s_and_b64 vcc, exec, vcc
+; CHECK: s_cbranch_vccz [[UNREACHABLE:BB[0-9]+_[0-9]+]]
+
+; CHECK: [[UNREACHABLE]]:
+; CHECK-NEXT: .Lfunc_end{{[0-9]+}}
+define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1) #0 {
+bb:
+  %tmp = fcmp ult float %arg1, 0.000000e+00
+  %tmp2 = fcmp ult float %arg, 0x3FCF5C2900000000
+  br i1 %tmp, label %bb6, label %bb3
+
+bb3:                                              ; preds = %bb
+  br i1 %tmp2, label %bb5, label %bb4
+
+bb4:                                              ; preds = %bb3
+  br i1 true, label %bb5, label %bb7
+
+bb5:                                              ; preds = %bb4, %bb3
+  unreachable
+
+bb6:                                              ; preds = %bb
+  call void @llvm.AMDGPU.kill(float -1.000000e+00)
+  unreachable
+
+bb7:                                              ; preds = %bb4
+  ret void
+}
+
 declare void @llvm.AMDGPU.kill(float) #0
 
 attributes #0 = { nounwind }