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Differential D22354

AVX-512: Fixed BT instruction selection on AVX-512
ClosedPublic

Authored by delena on Jul 14 2016, 6:57 AM.

Details

Reviewers
spatel
RKSimon
Commits
rG2c0780b8e5ce: AVX-512: Fixed BT instruction selection.
rL275950: AVX-512: Fixed BT instruction selection.
Summary

The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets.
But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1).

I added the new sequence (truncate (a >>n) to i1) to the BT pattern.

One more thing that required changes in TargetLowering.cpp is bad simplification of (truncate (a >>n) to i1) when we compare it to i1:

%tmp29 = lshr i32 %x, %n               
%tmp3 = and i32 1, %tmp29
%tmp4 = icmp ne i32 %tmp3, 1

is transferred to

 %tmp29 = lshr i32 %x, %n               
%tmp3 = trunc i32 %tmp29 to i1
%tmp4 = icmp eq i32 %tmp3, 0

and then the 'bt' instruction should be selected:

%tmp4 = bt %x, %n

Diff Detail

Repository
rL LLVM

Event Timeline

delena updated this revision to Diff 63963.Jul 14 2016, 6:57 AM
delena retitled this revision from to AVX-512: Fixed BT instruction selection on AVX-512.
delena updated this object.
delena added reviewers: spatel, RKSimon.
delena set the repository for this revision to rL LLVM.
delena added a subscriber: llvm-commits.
spatel added inline comments.Jul 14 2016, 10:27 AM
../lib/Target/X86/X86ISelLowering.cpp
15072–15091 ↗(On Diff #63963)

This is all copied code & comments; please add a helper function instead of duplicating. That should make it easier to read too.

../test/CodeGen/X86/bt.ll
2 ↗(On Diff #63963)

Specify the attribute(s) that are being testing, not a CPU model.
I updated this file at rL275439, so it would be easier to see the current codegen. But I don't know which flavor(s) of avx-512 are affected, so I did not add a RUN for it. It would be better to add that RUN ahead of this patch, so we can see exactly what tests are affected by your patch. Thanks!

delena marked 2 inline comments as done.Jul 17 2016, 2:04 AM

Sanjay, thanks a lot for the review. I'm uploading a new patch.

../lib/Target/X86/X86ISelLowering.cpp
15072–15091 ↗(On Diff #63963)

I'll upload the updated patch.

delena updated this revision to Diff 64244.Jul 17 2016, 2:10 AM
delena marked an inline comment as done.

The changes are made according to Sanjay's comments.

  1. Common code is hoisted to a separate function getBitTestCondition().
  2. The test case bt.ll shows what's done.
spatel accepted this revision.Jul 18 2016, 10:59 AM
spatel edited edge metadata.

LGTM.

../test/CodeGen/X86/bt.ll
28–33 ↗(On Diff #64244)

I removed all of these CHECK lines because I didn't think they added value for any test in this file (we know the correct 'bt' is generated already). If you agree, you could delete all of those checks again.

This revision is now accepted and ready to land.Jul 18 2016, 10:59 AM
Closed by commit rL275950: AVX-512: Fixed BT instruction selection. (authored by delena). · Explain WhyJul 19 2016, 12:21 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
SelectionDAG/
4 lines
Target/
X86/
84 lines
test/
CodeGen/
X86/
564 lines

Diff 64451

llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Show First 20 Lines • Show All 1,462 Lines • ▼ Show 20 Lines if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
// Make sure we're not losing bits from the constant. // Make sure we're not losing bits from the constant.
if (MinBits > 0 && if (MinBits > 0 &&
MinBits < C1.getBitWidth() && MinBits < C1.getBitWidth() &&
MinBits >= ReqdBits) { MinBits >= ReqdBits) {
EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
// Will get folded away. // Will get folded away.
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt); SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
if (MinBits == 1 && C1 == 1)
// Invert the condition.
return DAG.getSetCC(dl, VT, Trunc, DAG.getConstant(0, dl, MVT::i1),
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT); SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT);
return DAG.getSetCC(dl, VT, Trunc, C, Cond); return DAG.getSetCC(dl, VT, Trunc, C, Cond);
} }
// If truncating the setcc operands is not desirable, we can still // If truncating the setcc operands is not desirable, we can still
// simplify the expression in some cases: // simplify the expression in some cases:
// setcc ([sz]ext (setcc x, y, cc)), 0, setne) -> setcc (x, y, cc) // setcc ([sz]ext (setcc x, y, cc)), 0, setne) -> setcc (x, y, cc)
// setcc ([sz]ext (setcc x, y, cc)), 0, seteq) -> setcc (x, y, inv(cc)) // setcc ([sz]ext (setcc x, y, cc)), 0, seteq) -> setcc (x, y, inv(cc))
▲ Show 20 Lines • Show All 2,072 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 15,004 Lines • ▼ Show 20 Lines
/// CPU if a division's cost is not at least twice the cost of a multiplication. /// CPU if a division's cost is not at least twice the cost of a multiplication.
/// This is because we still need one division to calculate the reciprocal and /// This is because we still need one division to calculate the reciprocal and
/// then we need two multiplies by that reciprocal as replacements for the /// then we need two multiplies by that reciprocal as replacements for the
/// original divisions. /// original divisions.
unsigned X86TargetLowering::combineRepeatedFPDivisors() const { unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
return 2; return 2;
} }
/// Create a BT (Bit Test) node - Test bit \p BitNo in \p Src and set condition
/// according to equal/not-equal condition code \p CC.
static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC,
const SDLoc &dl, SelectionDAG &DAG) {
// If Src is i8, promote it to i32 with any_extend. There is no i8 BT
// instruction. Since the shift amount is in-range-or-undefined, we know
// that doing a bittest on the i32 value is ok. We extend to i32 because
// the encoding for the i16 version is larger than the i32 version.
// Also promote i16 to i32 for performance / code size reason.
if (Src.getValueType() == MVT::i8 || Src.getValueType() == MVT::i16)
Src = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Src);
// If the operand types disagree, extend the shift amount to match. Since
// BT ignores high bits (like shifts) we can use anyextend.
if (Src.getValueType() != BitNo.getValueType())
BitNo = DAG.getNode(ISD::ANY_EXTEND, dl, Src.getValueType(), BitNo);
SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, Src, BitNo);
X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
DAG.getConstant(Cond, dl, MVT::i8), BT);
}
/// Result of 'and' is compared against zero. Change to a BT node if possible. /// Result of 'and' is compared against zero. Change to a BT node if possible.
SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, static SDValue LowerAndToBT(SDValue And, ISD::CondCode CC,
const SDLoc &dl, SelectionDAG &DAG) const { const SDLoc &dl, SelectionDAG &DAG) {
SDValue Op0 = And.getOperand(0); SDValue Op0 = And.getOperand(0);
SDValue Op1 = And.getOperand(1); SDValue Op1 = And.getOperand(1);
if (Op0.getOpcode() == ISD::TRUNCATE) if (Op0.getOpcode() == ISD::TRUNCATE)
Op0 = Op0.getOperand(0); Op0 = Op0.getOperand(0);
if (Op1.getOpcode() == ISD::TRUNCATE) if (Op1.getOpcode() == ISD::TRUNCATE)
Op1 = Op1.getOperand(0); Op1 = Op1.getOperand(0);
SDValue LHS, RHS; SDValue LHS, RHS;
Show All 26 Lines if (Op0.getOpcode() == ISD::SHL) {
// Use BT if the immediate can't be encoded in a TEST instruction. // Use BT if the immediate can't be encoded in a TEST instruction.
if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
LHS = AndLHS; LHS = AndLHS;
RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType()); RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
} }
} }
if (LHS.getNode()) { if (LHS.getNode())
// If LHS is i8, promote it to i32 with any_extend. There is no i8 BT return getBitTestCondition(LHS, RHS, CC, dl, DAG);
// instruction. Since the shift amount is in-range-or-undefined, we know
// that doing a bittest on the i32 value is ok. We extend to i32 because
// the encoding for the i16 version is larger than the i32 version.
// Also promote i16 to i32 for performance / code size reason.
if (LHS.getValueType() == MVT::i8 ||
LHS.getValueType() == MVT::i16)
LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
// If the operand types disagree, extend the shift amount to match. Since return SDValue();
// BT ignores high bits (like shifts) we can use anyextend. }
if (LHS.getValueType() != RHS.getValueType())
RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); // Convert (truncate (srl X, N) to i1) to (bt X, N)
X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; static SDValue LowerTruncateToBT(SDValue Op, ISD::CondCode CC,
return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, const SDLoc &dl, SelectionDAG &DAG) {
DAG.getConstant(Cond, dl, MVT::i8), BT);
assert(Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1 &&
"Expected TRUNCATE to i1 node");
if (Op.getOperand(0).getOpcode() != ISD::SRL)
return SDValue();
SDValue ShiftRight = Op.getOperand(0);
return getBitTestCondition(ShiftRight.getOperand(0), ShiftRight.getOperand(1),
CC, dl, DAG);
} }
/// Result of 'and' or 'trunc to i1' is compared against zero.
/// Change to a BT node if possible.
SDValue X86TargetLowering::LowerToBT(SDValue Op, ISD::CondCode CC,
const SDLoc &dl, SelectionDAG &DAG) const {
if (Op.getOpcode() == ISD::AND)
return LowerAndToBT(Op, CC, dl, DAG);
if (Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1)
return LowerTruncateToBT(Op, CC, dl, DAG);
return SDValue(); return SDValue();
} }
/// Turns an ISD::CondCode into a value suitable for SSE floating-point mask /// Turns an ISD::CondCode into a value suitable for SSE floating-point mask
/// CMPs. /// CMPs.
static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0, static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
SDValue &Op1) { SDValue &Op1) {
unsigned SSECC; unsigned SSECC;
▲ Show 20 Lines • Show All 514 Lines • ▼ Show 20 LinesSDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
SDValue Op1 = Op.getOperand(1); SDValue Op1 = Op.getOperand(1);
SDLoc dl(Op); SDLoc dl(Op);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
// Optimize to BT if possible. // Optimize to BT if possible.
// Lower (X & (1 << N)) == 0 to BT(X, N). // Lower (X & (1 << N)) == 0 to BT(X, N).
// Lower ((X >>u N) & 1) != 0 to BT(X, N). // Lower ((X >>u N) & 1) != 0 to BT(X, N).
// Lower ((X >>s N) & 1) != 0 to BT(X, N). // Lower ((X >>s N) & 1) != 0 to BT(X, N).
if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && // Lower (trunc (X >> N) to i1) to BT(X, N).
isNullConstant(Op1) && if (Op0.hasOneUse() && isNullConstant(Op1) &&
(CC == ISD::SETEQ || CC == ISD::SETNE)) { (CC == ISD::SETEQ || CC == ISD::SETNE)) {
if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) { if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
if (VT == MVT::i1) { if (VT == MVT::i1) {
NewSetCC = DAG.getNode(ISD::AssertZext, dl, MVT::i8, NewSetCC, NewSetCC = DAG.getNode(ISD::AssertZext, dl, MVT::i8, NewSetCC,
DAG.getValueType(MVT::i1)); DAG.getValueType(MVT::i1));
return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC); return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
} }
return NewSetCC; return NewSetCC;
▲ Show 20 Lines • Show All 1,174 Lines • ▼ Show 20 Lines if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
} }
} }
} }
if (addTest) { if (addTest) {
// Look pass the truncate if the high bits are known zero. // Look pass the truncate if the high bits are known zero.
Cond = getCondAfterTruncWithZeroHighBitsInput(Cond, DAG); Cond = getCondAfterTruncWithZeroHighBitsInput(Cond, DAG);
// We know the result of AND is compared against zero. Try to match // We know the result is compared against zero. Try to match it to BT.
// it to BT. if (Cond.hasOneUse()) {
if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) { if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
CC = NewSetCC.getOperand(0); CC = NewSetCC.getOperand(0);
Cond = NewSetCC.getOperand(1); Cond = NewSetCC.getOperand(1);
addTest = false; addTest = false;
} }
} }
} }
▲ Show 20 Lines • Show All 15,111 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/bt.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck --check-prefix=CHECK --check-prefix=PENTIUM4 %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck --check-prefix=CHECK --check-prefix=AVX-512 %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s
; PR3253 ; PR3253
; The register+memory form of the BT instruction should be usable on ; The register+memory form of the BT instruction should be usable on
; pentium4, however it is currently disabled due to the register+memory ; pentium4, however it is currently disabled due to the register+memory
; form having different semantics than the register+register form. ; form having different semantics than the register+register form.
; Test these patterns: ; Test these patterns:
; (X & (1 << N)) != 0 --> BT(X, N). ; (X & (1 << N)) != 0 --> BT(X, N).
; ((X >>u N) & 1) != 0 --> BT(X, N). ; ((X >>u N) & 1) != 0 --> BT(X, N).
; as well as several variations: ; as well as several variations:
; - The second form can use an arithmetic shift. ; - The second form can use an arithmetic shift.
; - Either form can use == instead of !=. ; - Either form can use == instead of !=.
; - Either form can compare with an operand of the & ; - Either form can compare with an operand of the &
; instead of with 0. ; instead of with 0.
; - The comparison can be commuted (only cases where neither ; - The comparison can be commuted (only cases where neither
; operand is constant are included). ; operand is constant are included).
; - The and can be commuted. ; - The and can be commuted.
define void @test2(i32 %x, i32 %n) nounwind { define void @test2(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: test2: ; CHECK-LABEL: test2:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jb .LBB0_2 ; CHECK-NEXT: jb .LBB0_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB0_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: test2:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: testb $1, %dil
; AVX-512-NEXT: jne .LBB0_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB0_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = lshr i32 %x, %n %tmp29 = lshr i32 %x, %n
%tmp3 = and i32 %tmp29, 1 %tmp3 = and i32 %tmp29, 1
%tmp4 = icmp eq i32 %tmp3, 0 %tmp4 = icmp eq i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @test2b(i32 %x, i32 %n) nounwind { define void @test2b(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: test2b: ; CHECK-LABEL: test2b:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jb .LBB1_2 ; CHECK-NEXT: jb .LBB1_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB1_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: test2b:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: testb $1, %dil
; AVX-512-NEXT: jne .LBB1_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB1_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = lshr i32 %x, %n %tmp29 = lshr i32 %x, %n
%tmp3 = and i32 1, %tmp29 %tmp3 = and i32 1, %tmp29
%tmp4 = icmp eq i32 %tmp3, 0 %tmp4 = icmp eq i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @atest2(i32 %x, i32 %n) nounwind { define void @atest2(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: atest2: ; CHECK-LABEL: atest2:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jb .LBB2_2 ; CHECK-NEXT: jb .LBB2_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB2_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: atest2:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: testb $1, %dil
; AVX-512-NEXT: jne .LBB2_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB2_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = ashr i32 %x, %n %tmp29 = ashr i32 %x, %n
%tmp3 = and i32 %tmp29, 1 %tmp3 = and i32 %tmp29, 1
%tmp4 = icmp eq i32 %tmp3, 0 %tmp4 = icmp eq i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @atest2b(i32 %x, i32 %n) nounwind { define void @atest2b(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: atest2b: ; CHECK-LABEL: atest2b:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jb .LBB3_2 ; CHECK-NEXT: jb .LBB3_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB3_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: atest2b:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: testb $1, %dil
; AVX-512-NEXT: jne .LBB3_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB3_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = ashr i32 %x, %n %tmp29 = ashr i32 %x, %n
%tmp3 = and i32 1, %tmp29 %tmp3 = and i32 1, %tmp29
%tmp4 = icmp eq i32 %tmp3, 0 %tmp4 = icmp eq i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @test3(i32 %x, i32 %n) nounwind { define void @test3(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB4_2 ; CHECK-NEXT: jb .LBB4_2
; CHECK-NEXT: # BB#1: # %bb ;
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq foo
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .LBB4_2: # %UnifiedReturnBlock
; CHECK-NEXT: retq
entry: entry:
%tmp29 = shl i32 1, %n %tmp29 = shl i32 1, %n
%tmp3 = and i32 %tmp29, %x %tmp3 = and i32 %tmp29, %x
%tmp4 = icmp eq i32 %tmp3, 0 %tmp4 = icmp eq i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @test3b(i32 %x, i32 %n) nounwind { define void @test3b(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: test3b: ; CHECK-LABEL: test3b:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB5_2 ; CHECK-NEXT: jb .LBB5_2
; CHECK-NEXT: # BB#1: # %bb ;
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq foo
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .LBB5_2: # %UnifiedReturnBlock
; CHECK-NEXT: retq
entry: entry:
%tmp29 = shl i32 1, %n %tmp29 = shl i32 1, %n
%tmp3 = and i32 %x, %tmp29 %tmp3 = and i32 %x, %tmp29
%tmp4 = icmp eq i32 %tmp3, 0 %tmp4 = icmp eq i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @testne2(i32 %x, i32 %n) nounwind { define void @testne2(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: testne2: ; CHECK-LABEL: testne2:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jae .LBB6_2 ; CHECK-NEXT: jae .LBB6_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB6_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: testne2:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: testb $1, %dil
; AVX-512-NEXT: je .LBB6_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB6_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = lshr i32 %x, %n %tmp29 = lshr i32 %x, %n
%tmp3 = and i32 %tmp29, 1 %tmp3 = and i32 %tmp29, 1
%tmp4 = icmp ne i32 %tmp3, 0 %tmp4 = icmp ne i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @testne2b(i32 %x, i32 %n) nounwind { define void @testne2b(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: testne2b: ; CHECK-LABEL: testne2b:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jae .LBB7_2 ; CHECK-NEXT: jae .LBB7_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB7_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: testne2b:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: testb $1, %dil
; AVX-512-NEXT: je .LBB7_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB7_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = lshr i32 %x, %n %tmp29 = lshr i32 %x, %n
%tmp3 = and i32 1, %tmp29 %tmp3 = and i32 1, %tmp29
%tmp4 = icmp ne i32 %tmp3, 0 %tmp4 = icmp ne i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @atestne2(i32 %x, i32 %n) nounwind { define void @atestne2(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: atestne2: ; CHECK-LABEL: atestne2:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jae .LBB8_2 ; CHECK-NEXT: jae .LBB8_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB8_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: atestne2:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: testb $1, %dil
; AVX-512-NEXT: je .LBB8_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB8_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = ashr i32 %x, %n %tmp29 = ashr i32 %x, %n
%tmp3 = and i32 %tmp29, 1 %tmp3 = and i32 %tmp29, 1
%tmp4 = icmp ne i32 %tmp3, 0 %tmp4 = icmp ne i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @atestne2b(i32 %x, i32 %n) nounwind { define void @atestne2b(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: atestne2b: ; CHECK-LABEL: atestne2b:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jae .LBB9_2 ; CHECK-NEXT: jae .LBB9_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB9_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: atestne2b:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: testb $1, %dil
; AVX-512-NEXT: je .LBB9_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB9_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = ashr i32 %x, %n %tmp29 = ashr i32 %x, %n
%tmp3 = and i32 1, %tmp29 %tmp3 = and i32 1, %tmp29
%tmp4 = icmp ne i32 %tmp3, 0 %tmp4 = icmp ne i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @testne3(i32 %x, i32 %n) nounwind { define void @testne3(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: testne3: ; CHECK-LABEL: testne3:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB10_2 ; CHECK-NEXT: jae .LBB10_2
; CHECK-NEXT: # BB#1: # %bb ;
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq foo
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .LBB10_2: # %UnifiedReturnBlock
; CHECK-NEXT: retq
entry: entry:
%tmp29 = shl i32 1, %n %tmp29 = shl i32 1, %n
%tmp3 = and i32 %tmp29, %x %tmp3 = and i32 %tmp29, %x
%tmp4 = icmp ne i32 %tmp3, 0 %tmp4 = icmp ne i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @testne3b(i32 %x, i32 %n) nounwind { define void @testne3b(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: testne3b: ; CHECK-LABEL: testne3b:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB11_2 ; CHECK-NEXT: jae .LBB11_2
; CHECK-NEXT: # BB#1: # %bb ;
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq foo
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .LBB11_2: # %UnifiedReturnBlock
; CHECK-NEXT: retq
entry: entry:
%tmp29 = shl i32 1, %n %tmp29 = shl i32 1, %n
%tmp3 = and i32 %x, %tmp29 %tmp3 = and i32 %x, %tmp29
%tmp4 = icmp ne i32 %tmp3, 0 %tmp4 = icmp ne i32 %tmp3, 0
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @query2(i32 %x, i32 %n) nounwind { define void @query2(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: query2: ; CHECK-LABEL: query2:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jae .LBB12_2 ; CHECK-NEXT: jae .LBB12_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB12_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: query2:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: testb $1, %dil
; AVX-512-NEXT: je .LBB12_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB12_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = lshr i32 %x, %n %tmp29 = lshr i32 %x, %n
%tmp3 = and i32 %tmp29, 1 %tmp3 = and i32 %tmp29, 1
%tmp4 = icmp eq i32 %tmp3, 1 %tmp4 = icmp eq i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @query2b(i32 %x, i32 %n) nounwind { define void @query2b(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: query2b: ; CHECK-LABEL: query2b:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jae .LBB13_2 ; CHECK-NEXT: jae .LBB13_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB13_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: query2b:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: testb $1, %dil
; AVX-512-NEXT: je .LBB13_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB13_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = lshr i32 %x, %n %tmp29 = lshr i32 %x, %n
%tmp3 = and i32 1, %tmp29 %tmp3 = and i32 1, %tmp29
%tmp4 = icmp eq i32 %tmp3, 1 %tmp4 = icmp eq i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @aquery2(i32 %x, i32 %n) nounwind { define void @aquery2(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: aquery2: ; CHECK-LABEL: aquery2:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jae .LBB14_2 ; CHECK-NEXT: jae .LBB14_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB14_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: aquery2:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: testb $1, %dil
; AVX-512-NEXT: je .LBB14_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB14_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = ashr i32 %x, %n %tmp29 = ashr i32 %x, %n
%tmp3 = and i32 %tmp29, 1 %tmp3 = and i32 %tmp29, 1
%tmp4 = icmp eq i32 %tmp3, 1 %tmp4 = icmp eq i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @aquery2b(i32 %x, i32 %n) nounwind { define void @aquery2b(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: aquery2b: ; CHECK-LABEL: aquery2b:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jae .LBB15_2 ; CHECK-NEXT: jae .LBB15_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB15_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: aquery2b:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: testb $1, %dil
; AVX-512-NEXT: je .LBB15_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB15_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = ashr i32 %x, %n %tmp29 = ashr i32 %x, %n
%tmp3 = and i32 1, %tmp29 %tmp3 = and i32 1, %tmp29
%tmp4 = icmp eq i32 %tmp3, 1 %tmp4 = icmp eq i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @query3(i32 %x, i32 %n) nounwind { define void @query3(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: query3: ; CHECK-LABEL: query3:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB16_2 ; CHECK-NEXT: jae .LBB16_2
; CHECK-NEXT: # BB#1: # %bb ;
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq foo
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .LBB16_2: # %UnifiedReturnBlock
; CHECK-NEXT: retq
entry: entry:
%tmp29 = shl i32 1, %n %tmp29 = shl i32 1, %n
%tmp3 = and i32 %tmp29, %x %tmp3 = and i32 %tmp29, %x
%tmp4 = icmp eq i32 %tmp3, %tmp29 %tmp4 = icmp eq i32 %tmp3, %tmp29
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @query3b(i32 %x, i32 %n) nounwind { define void @query3b(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: query3b: ; CHECK-LABEL: query3b:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB17_2 ; CHECK-NEXT: jae .LBB17_2
; CHECK-NEXT: # BB#1: # %bb ;
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq foo
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .LBB17_2: # %UnifiedReturnBlock
; CHECK-NEXT: retq
entry: entry:
%tmp29 = shl i32 1, %n %tmp29 = shl i32 1, %n
%tmp3 = and i32 %x, %tmp29 %tmp3 = and i32 %x, %tmp29
%tmp4 = icmp eq i32 %tmp3, %tmp29 %tmp4 = icmp eq i32 %tmp3, %tmp29
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @query3x(i32 %x, i32 %n) nounwind { define void @query3x(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: query3x: ; CHECK-LABEL: query3x:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB18_2 ; CHECK-NEXT: jae .LBB18_2
; CHECK-NEXT: # BB#1: # %bb ;
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq foo
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .LBB18_2: # %UnifiedReturnBlock
; CHECK-NEXT: retq
entry: entry:
%tmp29 = shl i32 1, %n %tmp29 = shl i32 1, %n
%tmp3 = and i32 %tmp29, %x %tmp3 = and i32 %tmp29, %x
%tmp4 = icmp eq i32 %tmp29, %tmp3 %tmp4 = icmp eq i32 %tmp29, %tmp3
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @query3bx(i32 %x, i32 %n) nounwind { define void @query3bx(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: query3bx: ; CHECK-LABEL: query3bx:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jae .LBB19_2 ; CHECK-NEXT: jae .LBB19_2
; CHECK-NEXT: # BB#1: # %bb ;
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq foo
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .LBB19_2: # %UnifiedReturnBlock
; CHECK-NEXT: retq
entry: entry:
%tmp29 = shl i32 1, %n %tmp29 = shl i32 1, %n
%tmp3 = and i32 %x, %tmp29 %tmp3 = and i32 %x, %tmp29
%tmp4 = icmp eq i32 %tmp29, %tmp3 %tmp4 = icmp eq i32 %tmp29, %tmp3
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @queryne2(i32 %x, i32 %n) nounwind { define void @queryne2(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: queryne2: ; CHECK-LABEL: queryne2:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jb .LBB20_2 ; CHECK-NEXT: jb .LBB20_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB20_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: queryne2:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: andl $1, %edi
; AVX-512-NEXT: kmovw %edi, %k0
; AVX-512-NEXT: kxnorw %k0, %k0, %k1
; AVX-512-NEXT: kshiftrw $15, %k1, %k1
; AVX-512-NEXT: kxorw %k1, %k0, %k0
; AVX-512-NEXT: kmovw %k0, %eax
; AVX-512-NEXT: testb %al, %al
; AVX-512-NEXT: je .LBB20_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB20_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = lshr i32 %x, %n %tmp29 = lshr i32 %x, %n
%tmp3 = and i32 %tmp29, 1 %tmp3 = and i32 %tmp29, 1
%tmp4 = icmp ne i32 %tmp3, 1 %tmp4 = icmp ne i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @queryne2b(i32 %x, i32 %n) nounwind { define void @queryne2b(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: queryne2b: ; CHECK-LABEL: queryne2b:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jb .LBB21_2 ; CHECK-NEXT: jb .LBB21_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB21_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: queryne2b:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: andl $1, %edi
; AVX-512-NEXT: kmovw %edi, %k0
; AVX-512-NEXT: kxnorw %k0, %k0, %k1
; AVX-512-NEXT: kshiftrw $15, %k1, %k1
; AVX-512-NEXT: kxorw %k1, %k0, %k0
; AVX-512-NEXT: kmovw %k0, %eax
; AVX-512-NEXT: testb %al, %al
; AVX-512-NEXT: je .LBB21_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB21_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = lshr i32 %x, %n %tmp29 = lshr i32 %x, %n
%tmp3 = and i32 1, %tmp29 %tmp3 = and i32 1, %tmp29
%tmp4 = icmp ne i32 %tmp3, 1 %tmp4 = icmp ne i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @aqueryne2(i32 %x, i32 %n) nounwind { define void @aqueryne2(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: aqueryne2: ; CHECK-LABEL: aqueryne2:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jb .LBB22_2 ; CHECK-NEXT: jb .LBB22_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB22_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: aqueryne2:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: andl $1, %edi
; AVX-512-NEXT: kmovw %edi, %k0
; AVX-512-NEXT: kxnorw %k0, %k0, %k1
; AVX-512-NEXT: kshiftrw $15, %k1, %k1
; AVX-512-NEXT: kxorw %k1, %k0, %k0
; AVX-512-NEXT: kmovw %k0, %eax
; AVX-512-NEXT: testb %al, %al
; AVX-512-NEXT: je .LBB22_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB22_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = ashr i32 %x, %n %tmp29 = ashr i32 %x, %n
%tmp3 = and i32 %tmp29, 1 %tmp3 = and i32 %tmp29, 1
%tmp4 = icmp ne i32 %tmp3, 1 %tmp4 = icmp ne i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @aqueryne2b(i32 %x, i32 %n) nounwind { define void @aqueryne2b(i32 %x, i32 %n) nounwind {
; PENTIUM4-LABEL: aqueryne2b: ; CHECK-LABEL: aqueryne2b:
; PENTIUM4: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; PENTIUM4-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; PENTIUM4-NEXT: jb .LBB23_2 ; CHECK-NEXT: jb .LBB23_2
; PENTIUM4-NEXT: # BB#1: # %bb ;
; PENTIUM4-NEXT: pushq %rax
; PENTIUM4-NEXT: callq foo
; PENTIUM4-NEXT: popq %rax
; PENTIUM4-NEXT: .LBB23_2: # %UnifiedReturnBlock
; PENTIUM4-NEXT: retq
;
; AVX-512-LABEL: aqueryne2b:
; AVX-512: # BB#0: # %entry
; AVX-512-NEXT: movl %esi, %ecx
; AVX-512-NEXT: shrl %cl, %edi
; AVX-512-NEXT: andl $1, %edi
; AVX-512-NEXT: kmovw %edi, %k0
; AVX-512-NEXT: kxnorw %k0, %k0, %k1
; AVX-512-NEXT: kshiftrw $15, %k1, %k1
; AVX-512-NEXT: kxorw %k1, %k0, %k0
; AVX-512-NEXT: kmovw %k0, %eax
; AVX-512-NEXT: testb %al, %al
; AVX-512-NEXT: je .LBB23_2
; AVX-512-NEXT: # BB#1: # %bb
; AVX-512-NEXT: pushq %rax
; AVX-512-NEXT: callq foo
; AVX-512-NEXT: popq %rax
; AVX-512-NEXT: .LBB23_2: # %UnifiedReturnBlock
; AVX-512-NEXT: retq
entry: entry:
%tmp29 = ashr i32 %x, %n %tmp29 = ashr i32 %x, %n
%tmp3 = and i32 1, %tmp29 %tmp3 = and i32 1, %tmp29
%tmp4 = icmp ne i32 %tmp3, 1 %tmp4 = icmp ne i32 %tmp3, 1
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @queryne3(i32 %x, i32 %n) nounwind { define void @queryne3(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: queryne3: ; CHECK-LABEL: queryne3:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB24_2 ; CHECK-NEXT: jb .LBB24_2
; CHECK-NEXT: # BB#1: # %bb ;
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq foo
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .LBB24_2: # %UnifiedReturnBlock
; CHECK-NEXT: retq
entry: entry:
%tmp29 = shl i32 1, %n %tmp29 = shl i32 1, %n
%tmp3 = and i32 %tmp29, %x %tmp3 = and i32 %tmp29, %x
%tmp4 = icmp ne i32 %tmp3, %tmp29 %tmp4 = icmp ne i32 %tmp3, %tmp29
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @queryne3b(i32 %x, i32 %n) nounwind { define void @queryne3b(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: queryne3b: ; CHECK-LABEL: queryne3b:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB25_2 ; CHECK-NEXT: jb .LBB25_2
; CHECK-NEXT: # BB#1: # %bb ;
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq foo
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .LBB25_2: # %UnifiedReturnBlock
; CHECK-NEXT: retq
entry: entry:
%tmp29 = shl i32 1, %n %tmp29 = shl i32 1, %n
%tmp3 = and i32 %x, %tmp29 %tmp3 = and i32 %x, %tmp29
%tmp4 = icmp ne i32 %tmp3, %tmp29 %tmp4 = icmp ne i32 %tmp3, %tmp29
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @queryne3x(i32 %x, i32 %n) nounwind { define void @queryne3x(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: queryne3x: ; CHECK-LABEL: queryne3x:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB26_2 ; CHECK-NEXT: jb .LBB26_2
; CHECK-NEXT: # BB#1: # %bb ;
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq foo
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .LBB26_2: # %UnifiedReturnBlock
; CHECK-NEXT: retq
entry: entry:
%tmp29 = shl i32 1, %n %tmp29 = shl i32 1, %n
%tmp3 = and i32 %tmp29, %x %tmp3 = and i32 %tmp29, %x
%tmp4 = icmp ne i32 %tmp29, %tmp3 %tmp4 = icmp ne i32 %tmp29, %tmp3
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @queryne3bx(i32 %x, i32 %n) nounwind { define void @queryne3bx(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: queryne3bx: ; CHECK-LABEL: queryne3bx:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: jb .LBB27_2 ; CHECK-NEXT: jb .LBB27_2
; CHECK-NEXT: # BB#1: # %bb ;
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq foo
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .LBB27_2: # %UnifiedReturnBlock
; CHECK-NEXT: retq
entry: entry:
%tmp29 = shl i32 1, %n %tmp29 = shl i32 1, %n
%tmp3 = and i32 %x, %tmp29 %tmp3 = and i32 %x, %tmp29
%tmp4 = icmp ne i32 %tmp29, %tmp3 %tmp4 = icmp ne i32 %tmp29, %tmp3
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
declare void @foo() declare void @foo()
define zeroext i1 @invert(i32 %flags, i32 %flag) nounwind { define zeroext i1 @invert(i32 %flags, i32 %flag) nounwind {
; CHECK-LABEL: invert: ; CHECK-LABEL: invert:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: notl %edi ; CHECK-NEXT: notl %edi
; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: btl %esi, %edi
; CHECK-NEXT: setb %al ; CHECK-NEXT: setb %al
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
%neg = xor i32 %flags, -1 %neg = xor i32 %flags, -1
%shl = shl i32 1, %flag %shl = shl i32 1, %flag
%and = and i32 %shl, %neg %and = and i32 %shl, %neg
%tobool = icmp ne i32 %and, 0 %tobool = icmp ne i32 %and, 0
ret i1 %tobool ret i1 %tobool
} }