[InstCombine] reverse canonicalization of xor(zext i1 A), 1 <---> zext(not i1 A, true) (PR28476)

[spatel]

Summary

We discussed this a bit in D21899.

By creating the official 'not' IR construct, we can:

1. Remove DeMorgan-matching code that was added specifically to work-around the missing transform in http://reviews.llvm.org/rL248634.
2. Make the DeMorgan transform for vectors too.
3. Fix PR28476: https://llvm.org/bugs/show_bug.cgi?id=28476

I don't see any other transforms that were relying on the previous transform, so I think it's safe to replace it.

The test changes outside of the demorgan-zext.ll file look neutral to me; those just show that the xor gets pulled ahead of the zext. But we could make the argument that those transforms actually are improvements too because doing logic ops in a smaller type should always provide >= optimization opportunity to later passes.

[eli.friedman]

Is "zext(a_bool ^ true) ^ 2" canonical, or is "zext(a_bool) ^ 3"? Either way, you're missing a transform.

[spatel]

In D22271#482114, @eli.friedman wrote:

Is "zext(a_bool ^ true) ^ 2" canonical, or is "zext(a_bool) ^ 3"? Either way, you're missing a transform.

Ah, I missed the point that you were making from your earlier comment. I'd say the ^3 version is canonical because less-instructions is better than 'not'.

I added tests for these patterns in rL275297 and rL275302 .

[spatel]

Patch updated:
The deletions are identical to the earlier rev: (a) the specialized DeMorgan matcher (b) the canonicalization of zext before xor i1.

Instead of limiting this to only xor i1+zext, however, move any bitwise logic with a constant to the source type of the zext if the constant fits. I don't think there's any reason to limit the transform to i1 types. The vector case for doing this kind of transform came up in:
https://llvm.org/bugs/show_bug.cgi?id=28160

D22421 transforms the patterns that Eli noted.
D22477 handled the only existing test that I found that would have regressed from this change.

[spatel]

Patch updated:
The previous rev forgot to delete some 'FIXME' comments from the test files.

[eli.friedman]

LGTM.

llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

static Instruction *matchDeMorgansLaws(BinaryOperator &I,
   if (Value *Op0NotVal = dyn_castNotVal(Op0))
     if (Value *Op1NotVal = dyn_castNotVal(Op1))
       if (Op0->hasOneUse() && Op1->hasOneUse()) {
         Value *LogicOp = Builder->CreateBinOp(Opcode, Op0NotVal, Op1NotVal,
                                               I.getName() + ".demorgan");
         return BinaryOperator::CreateNot(LogicOp);
       }
 
-  // De Morgan's Law in disguise:
-  // (zext(bool A) ^ 1) & (zext(bool B) ^ 1) -> zext(~(A | B))
-  // (zext(bool A) ^ 1) | (zext(bool B) ^ 1) -> zext(~(A & B))
-  Value *A = nullptr;
-  Value *B = nullptr;
-  ConstantInt *C1 = nullptr;
-  if (match(Op0, m_OneUse(m_Xor(m_ZExt(m_Value(A)), m_ConstantInt(C1)))) &&
-      match(Op1, m_OneUse(m_Xor(m_ZExt(m_Value(B)), m_Specific(C1))))) {
-    // TODO: This check could be loosened to handle different type sizes.
-    // Alternatively, we could fix the definition of m_Not to recognize a not
-    // operation hidden by a zext?
-    if (A->getType()->isIntegerTy(1) && B->getType()->isIntegerTy(1) &&
-        C1->isOne()) {
-      Value *LogicOp = Builder->CreateBinOp(Opcode, A, B,
-                                            I.getName() + ".demorgan");
-      Value *Not = Builder->CreateNot(LogicOp);
-      return CastInst::CreateZExtOrBitCast(Not, I.getType());
-    }
-  }
-
   return nullptr;
 }
 
 bool InstCombiner::shouldOptimizeCast(CastInst *CI) {
   Value *CastSrc = CI->getOperand(0);
 
   // Noop casts and casts of constants should be eliminated trivially.
   if (CI->getSrcTy() == CI->getDestTy() || isa<Constant>(CastSrc))
Instruction *InstCombiner::foldCastedBitwiseLogic(BinaryOperator &I) {
   Value *BC = nullptr;
   Constant *C = nullptr;
   if ((match(Op0, m_BitCast(m_Value(BC))) && match(Op1, m_Constant(C)))) {
     Value *NewConstant = ConstantExpr::getBitCast(C, SrcTy);
     Value *NewOp = Builder->CreateBinOp(LogicOpc, BC, NewConstant, I.getName());
     return CastInst::CreateBitOrPointerCast(NewOp, DestTy);
   }
 
+  // Similarly, if one operand is zexted and the other is a constant, move the
+  // logic operation ahead of the zext if the constant is unchanged in the
+  // smaller source type. Performing the logic in a smaller type may provide
+  // more information to later folds, and the smaller logic instruction may be
+  // cheaper (particularly in the case of vectors).
+  Value *X;
+  if (match(Op0, m_OneUse(m_ZExt(m_Value(X)))) && match(Op1, m_Constant(C))) {
+    Constant *TruncC = ConstantExpr::getTrunc(C, SrcTy);
+    Constant *ZextTruncC = ConstantExpr::getZExt(TruncC, DestTy);
+    if (ZextTruncC == C) {
+      // LogicOpc (zext X), C --> zext (LogicOpc X, C)
+      Value *NewOp = Builder->CreateBinOp(LogicOpc, X, TruncC);
+      return new ZExtInst(NewOp, DestTy);
+    }
+  }
+
   CastInst *Cast1 = dyn_cast<CastInst>(Op1);
   if (!Cast1)
     return nullptr;
 
   // Both operands of the logic operation are casts. The casts must be of the
   // same type for reduction.
   auto CastOpcode = Cast0->getOpcode();
   if (CastOpcode != Cast1->getOpcode() || SrcTy != Cast1->getSrcTy())

llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp

Instruction *InstCombiner::visitZExt(ZExtInst &CI) {
   Value *And;
   if (SrcI && match(SrcI, m_OneUse(m_Xor(m_Value(And), m_Constant(C)))) &&
       match(And, m_OneUse(m_And(m_Trunc(m_Value(X)), m_Specific(C)))) &&
       X->getType() == CI.getType()) {
     Constant *ZC = ConstantExpr::getZExt(C, CI.getType());
     return BinaryOperator::CreateXor(Builder->CreateAnd(X, ZC), ZC);
   }
 
-  // zext (xor i1 X, true) to i32  --> xor (zext i1 X to i32), 1
-  if (SrcI && SrcI->hasOneUse() &&
-      SrcI->getType()->getScalarType()->isIntegerTy(1) &&
-      match(SrcI, m_Not(m_Value(X))) && (!X->hasOneUse() || !isa<CmpInst>(X))) {
-    Value *New = Builder->CreateZExt(X, CI.getType());
-    return BinaryOperator::CreateXor(New, ConstantInt::get(CI.getType(), 1));
-  }
-
   return nullptr;
 }
 
 /// Transform (sext icmp) to bitwise / integer operations to eliminate the icmp.
 Instruction *InstCombiner::transformSExtICmp(ICmpInst *ICI, Instruction &CI) {
   Value *Op0 = ICI->getOperand(0), *Op1 = ICI->getOperand(1);
   ICmpInst::Predicate Pred = ICI->getPredicate();
 

llvm/trunk/test/Transforms/InstCombine/apint-select.ll

 ; CHECK-NEXT:    ret i41 [[V]]
 ;
   %V = select i1 %C, i41 -1, i41 0
   ret i41 %V
 }
 
 define i999 @not_zext(i1 %C) {
 ; CHECK-LABEL: @not_zext(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i1 %C to i999
-; CHECK-NEXT:    [[V:%.*]] = xor i999 [[TMP1]], 1
+; CHECK-NEXT:    [[NOT_C:%.*]] = xor i1 %C, true
+; CHECK-NEXT:    [[V:%.*]] = zext i1 [[NOT_C]] to i999
 ; CHECK-NEXT:    ret i999 [[V]]
 ;
   %V = select i1 %C, i999 0, i999 1
   ret i999 %V
 }
 
 define i999 @not_sext(i1 %C) {
 ; CHECK-LABEL: @not_sext(

 ; CHECK-NEXT:    ret <2 x i32> [[V]]
 ;
   %V = select <2 x i1> %C, <2 x i32> <i32 -1, i32 -1>, <2 x i32> <i32 0, i32 0>
   ret <2 x i32> %V
 }
 
 define <2 x i999> @not_zext_vec(<2 x i1> %C) {
 ; CHECK-LABEL: @not_zext_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext <2 x i1> %C to <2 x i999>
-; CHECK-NEXT:    [[V:%.*]] = xor <2 x i999> [[TMP1]], <i999 1, i999 1>
+; CHECK-NEXT:    [[NOT_C:%.*]] = xor <2 x i1> %C, <i1 true, i1 true>
+; CHECK-NEXT:    [[V:%.*]] = zext <2 x i1> [[NOT_C]] to <2 x i999>
 ; CHECK-NEXT:    ret <2 x i999> [[V]]
 ;
   %V = select <2 x i1> %C, <2 x i999> <i999 0, i999 0>, <2 x i999> <i999 1, i999 1>
   ret <2 x i999> %V
 }
 
 define <2 x i64> @not_sext_vec(<2 x i1> %C) {
 ; CHECK-LABEL: @not_sext_vec(

llvm/trunk/test/Transforms/InstCombine/assoc-cast-assoc.ll

;
   %op2 = or <2 x i32> %cast, <i32 1, i32 5>
   ret <2 x i32> %op2
 }
 
 ; Unlike the rest, this case is handled by SimplifyDemandedBits / ShrinkDemandedConstant.
 
 define i5 @AndZextAnd(i3 %a) {
 ; CHECK-LABEL: @AndZextAnd(
-; CHECK-NEXT:    [[CAST:%.*]] = zext i3 %a to i5
-; CHECK-NEXT:    [[OP2:%.*]] = and i5 [[CAST]], 2
+; CHECK-NEXT:    [[TMP1:%.*]] = and i3 %a, 2
+; CHECK-NEXT:    [[OP2:%.*]] = zext i3 [[TMP1]] to i5
 ; CHECK-NEXT:    ret i5 [[OP2]]
 ;
   %op1 = and i3 %a, 3
   %cast = zext i3 %op1 to i5
   %op2 = and i5 %cast, 14
   ret i5 %op2
 }
 
 define <2 x i32> @AndZextAndVec(<2 x i8> %a) {
 ; CHECK-LABEL: @AndZextAndVec(
-; CHECK-NEXT:    [[CAST:%.*]] = zext <2 x i8> %a to <2 x i32>
-; CHECK-NEXT:    [[OP2:%.*]] = and <2 x i32> [[CAST]], <i32 5, i32 0>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i8> %a, <i8 5, i8 0>
+; CHECK-NEXT:    [[OP2:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[OP2]]
 ;
   %op1 = and <2 x i8> %a, <i8 7, i8 0>
   %cast = zext <2 x i8> %op1 to <2 x i32>
   %op2 = and <2 x i32> %cast, <i32 261, i32 1>
   ret <2 x i32> %op2
 }
 

llvm/trunk/test/Transforms/InstCombine/cast.ll

;
   %C = or i16 %B, -32574
   %D = and i16 %C, -25350
   %E = zext i16 %D to i32
   ret i32 %E
 }
 
 define i64 @test53(i32 %A) {
 ; CHECK-LABEL: @test53(
-; CHECK-NEXT:    [[B:%.*]] = zext i32 %A to i64
-; CHECK-NEXT:    [[C:%.*]] = and i64 [[B]], 7224
-; CHECK-NEXT:    [[D:%.*]] = or i64 [[C]], 32962
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 %A, 7224
+; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[TMP1]], 32962
+; CHECK-NEXT:    [[D:%.*]] = zext i32 [[TMP2]] to i64
 ; CHECK-NEXT:    ret i64 [[D]]
 ;
   %B = trunc i32 %A to i16
   %C = or i16 %B, -32574
   %D = and i16 %C, -25350
   %E = zext i16 %D to i64
   ret i64 %E
 }
;
   %C = or i16 %B, -32574
   %D = and i16 %C, -25350
   %E = sext i16 %D to i32
   ret i32 %E
 }
 
 define i64 @test55(i32 %A) {
 ; CHECK-LABEL: @test55(
-; CHECK-NEXT:    [[B:%.*]] = zext i32 %A to i64
-; CHECK-NEXT:    [[C:%.*]] = and i64 [[B]], 7224
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 %A, 7224
+; CHECK-NEXT:    [[C:%.*]] = zext i32 [[TMP1]] to i64
 ; CHECK-NEXT:    [[D:%.*]] = or i64 [[C]], -32574
 ; CHECK-NEXT:    ret i64 [[D]]
 ;
   %B = trunc i32 %A to i16
   %C = or i16 %B, -32574
   %D = and i16 %C, -25350
   %E = sext i16 %D to i64
   ret i64 %E

llvm/trunk/test/Transforms/InstCombine/demorgan-zext.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 ; PR22723: Recognize De Morgan's Laws when obfuscated by zexts.
 
 define i32 @demorgan_or(i1 %X, i1 %Y) {
 ; CHECK-LABEL: @demorgan_or(
-; CHECK-NEXT:    [[OR_DEMORGAN:%.*]] = and i1 %X, %Y
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i1 [[OR_DEMORGAN]] to i32
-; CHECK-NEXT:    [[OR:%.*]] = xor i32 [[TMP1]], 1
+; CHECK-NEXT:    [[OR1_DEMORGAN:%.*]] = and i1 %X, %Y
+; CHECK-NEXT:    [[OR1:%.*]] = xor i1 [[OR1_DEMORGAN]], true
+; CHECK-NEXT:    [[OR:%.*]] = zext i1 [[OR:%.*]]1 to i32
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
   %zextX = zext i1 %X to i32
   %zextY = zext i1 %Y to i32
   %notX  = xor i32 %zextX, 1
   %notY  = xor i32 %zextY, 1
   %or    = or i32 %notX, %notY
   ret i32 %or
 }
 
 define i32 @demorgan_and(i1 %X, i1 %Y) {
 ; CHECK-LABEL: @demorgan_and(
-; CHECK-NEXT:    [[AND_DEMORGAN:%.*]] = or i1 %X, %Y
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i1 [[AND_DEMORGAN]] to i32
-; CHECK-NEXT:    [[AND:%.*]] = xor i32 [[TMP1]], 1
+; CHECK-NEXT:    [[AND1_DEMORGAN:%.*]] = or i1 %X, %Y
+; CHECK-NEXT:    [[AND1:%.*]] = xor i1 [[AND1_DEMORGAN]], true
+; CHECK-NEXT:    [[AND:%.*]] = zext i1 [[AND:%.*]]1 to i32
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %zextX = zext i1 %X to i32
   %zextY = zext i1 %Y to i32
   %notX  = xor i32 %zextX, 1
   %notY  = xor i32 %zextY, 1
   %and   = and i32 %notX, %notY
   ret i32 %and
 }
 
-; FIXME: Vectors should get the same transform.
-
 define <2 x i32> @demorgan_or_vec(<2 x i1> %X, <2 x i1> %Y) {
 ; CHECK-LABEL: @demorgan_or_vec(
-; CHECK-NEXT:    [[ZEXTX:%.*]] = zext <2 x i1> %X to <2 x i32>
-; CHECK-NEXT:    [[ZEXTY:%.*]] = zext <2 x i1> %Y to <2 x i32>
-; CHECK-NEXT:    [[NOTX:%.*]] = xor <2 x i32> [[ZEXTX]], <i32 1, i32 1>
-; CHECK-NEXT:    [[NOTY:%.*]] = xor <2 x i32> [[ZEXTY]], <i32 1, i32 1>
-; CHECK-NEXT:    [[OR:%.*]] = or <2 x i32> [[NOTX]], [[NOTY]]
+; CHECK-NEXT:    [[OR1_DEMORGAN:%.*]] = and <2 x i1> %X, %Y
+; CHECK-NEXT:    [[OR1:%.*]] = xor <2 x i1> [[OR1_DEMORGAN]], <i1 true, i1 true>
+; CHECK-NEXT:    [[OR:%.*]] = zext <2 x i1> [[OR:%.*]]1 to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[OR]]
 ;
   %zextX = zext <2 x i1> %X to <2 x i32>
   %zextY = zext <2 x i1> %Y to <2 x i32>
   %notX  = xor <2 x i32> %zextX, <i32 1, i32 1>
   %notY  = xor <2 x i32> %zextY, <i32 1, i32 1>
   %or    = or <2 x i32> %notX, %notY
   ret <2 x i32> %or
 }
 
 define <2 x i32> @demorgan_and_vec(<2 x i1> %X, <2 x i1> %Y) {
 ; CHECK-LABEL: @demorgan_and_vec(
-; CHECK-NEXT:    [[ZEXTX:%.*]] = zext <2 x i1> %X to <2 x i32>
-; CHECK-NEXT:    [[ZEXTY:%.*]] = zext <2 x i1> %Y to <2 x i32>
-; CHECK-NEXT:    [[NOTX:%.*]] = xor <2 x i32> [[ZEXTX]], <i32 1, i32 1>
-; CHECK-NEXT:    [[NOTY:%.*]] = xor <2 x i32> [[ZEXTY]], <i32 1, i32 1>
-; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[NOTX]], [[NOTY]]
+; CHECK-NEXT:    [[AND1_DEMORGAN:%.*]] = or <2 x i1> %X, %Y
+; CHECK-NEXT:    [[AND1:%.*]] = xor <2 x i1> [[AND1_DEMORGAN]], <i1 true, i1 true>
+; CHECK-NEXT:    [[AND:%.*]] = zext <2 x i1> [[AND:%.*]]1 to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[AND]]
 ;
   %zextX = zext <2 x i1> %X to <2 x i32>
   %zextY = zext <2 x i1> %Y to <2 x i32>
   %notX  = xor <2 x i32> %zextX, <i32 1, i32 1>
   %notY  = xor <2 x i32> %zextY, <i32 1, i32 1>
   %and   = and <2 x i32> %notX, %notY
   ret <2 x i32> %and
 }
 
-; FIXME: If the xor was canonicalized to a 'not', then this would simplify.
-
 define i32 @PR28476(i32 %x, i32 %y) {
 ; CHECK-LABEL: @PR28476(
-; CHECK-NEXT:    [[CMP0:%.*]] = icmp ne i32 %x, 0
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 %y, 0
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[CMP0]], [[CMP1]]
-; CHECK-NEXT:    [[ZEXT:%.*]] = zext i1 [[AND]] to i32
-; CHECK-NEXT:    [[COND:%.*]] = xor i32 [[ZEXT]], 1
+; CHECK-NEXT:    [[NOTLHS:%.*]] = icmp eq i32 %x, 0
+; CHECK-NEXT:    [[NOTRHS:%.*]] = icmp eq i32 %y, 0
+; CHECK-NEXT:    [[TMP1:%.*]] = or i1 [[NOTRHS]], [[NOTLHS]]
+; CHECK-NEXT:    [[COND:%.*]] = zext i1 [[TMP1]] to i32
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp0 = icmp ne i32 %x, 0
   %cmp1 = icmp ne i32 %y, 0
   %and = and i1 %cmp0, %cmp1
   %zext = zext i1 %and to i32
   %cond = xor i32 %zext, 1
   ret i32 %cond
 }
 

llvm/trunk/test/Transforms/InstCombine/select.ll

 ; CHECK-LABEL: @test12a(
 ; CHECK: %b = zext i1 %cond to i32
 ; CHECK: %c = ashr i32 %a, %b
 ; CHECK: ret i32 %c
 }
 
 define i32 @test12b(i1 %cond, i32 %a) {
 ; CHECK-LABEL: @test12b(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i1 %cond to i32
-; CHECK-NEXT:    [[B:%.*]] = xor i32 [[TMP1]], 1
+; CHECK-NEXT:    [[NOT_COND:%.*]] = xor i1 %cond, true
+; CHECK-NEXT:    [[B:%.*]] = zext i1 [[NOT_COND]] to i32
 ; CHECK-NEXT:    [[D:%.*]] = ashr i32 %a, [[B]]
 ; CHECK-NEXT:    ret i32 [[D]]
 ;
   %b = ashr i32 %a, 1
   %d = select i1 %cond, i32 %a, i32 %b
   ret i32 %d
 }
 
define i64 @select_icmp_x_and_8_ne_0_y_xor_8(i32 %x, i64 %y) {
   %xor = xor i64 %y, 8
   %xor.y = select i1 %cmp, i64 %xor, i64 %y
   ret i64 %xor.y
 }
 
 define i64 @select_icmp_x_and_8_ne_0_y_or_8(i32 %x, i64 %y) {
 ; CHECK-LABEL: @select_icmp_x_and_8_ne_0_y_or_8(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 %x, 8
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[AND]] to i64
-; CHECK-NEXT:    [[TMP2:%.*]] = xor i64 [[TMP1]], 8
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[AND]], 8
+; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
 ; CHECK-NEXT:    [[TMP3:%.*]] = or i64 [[TMP2]], %y
 ; CHECK-NEXT:    ret i64 [[TMP3]]
 ;
   %and = and i32 %x, 8
   %cmp = icmp eq i32 %and, 0
   %or = or i64 %y, 8
   %or.y = select i1 %cmp, i64 %or, i64 %y
   ret i64 %or.y

llvm/trunk/test/Transforms/InstCombine/zeroext-and-reduce.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i32 @test1(i8 %X) {
 ; CHECK-LABEL: @test1(
-; CHECK-NEXT:    [[Y:%.*]] = zext i8 %X to i32
-; CHECK-NEXT:    [[Z:%.*]] = and i32 [[Y]], 8
+; CHECK-NEXT:    [[TMP1:%.*]] = and i8 %X, 8
+; CHECK-NEXT:    [[Z:%.*]] = zext i8 [[TMP1]] to i32
 ; CHECK-NEXT:    ret i32 [[Z]]
 ;
   %Y = zext i8 %X to i32
   %Z = and i32 %Y, 65544
   ret i32 %Z
 }
 
 

llvm/trunk/test/Transforms/InstCombine/zext.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i64 @test_sext_zext(i16 %A) {
 ; CHECK-LABEL: @test_sext_zext(
 ; CHECK-NEXT:    [[C2:%.*]] = zext i16 %A to i64
 ; CHECK-NEXT:    ret i64 [[C2]]
 ;
   %c1 = zext i16 %A to i32
   %c2 = sext i32 %c1 to i64
   ret i64 %c2
 }
 
 define <2 x i64> @test2(<2 x i1> %A) {
 ; CHECK-LABEL: @test2(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext <2 x i1> %A to <2 x i64>
-; CHECK-NEXT:    [[ZEXT:%.*]] = xor <2 x i64> [[TMP1]], <i64 1, i64 1>
+; CHECK-NEXT:    [[XOR:%.*]] = xor <2 x i1> %A, <i1 true, i1 true>
+; CHECK-NEXT:    [[ZEXT:%.*]] = zext <2 x i1> [[XOR]] to <2 x i64>
 ; CHECK-NEXT:    ret <2 x i64> [[ZEXT]]
 ;
   %xor = xor <2 x i1> %A, <i1 true, i1 true>
   %zext = zext <2 x i1> %xor to <2 x i64>
   ret <2 x i64> %zext
 }
 
 define <2 x i64> @test3(<2 x i64> %A) {

 ;
   %trunc = trunc <2 x i64> %A to <2 x i32>
   %and = and <2 x i32> %trunc, <i32 23, i32 42>
   %xor = xor <2 x i32> %and, <i32 23, i32 42>
   %zext = zext <2 x i32> %xor to <2 x i64>
   ret <2 x i64> %zext
 }
 
-; FIXME: If the xor was done in the smaller type, the back-to-back zexts would get combined.
-
 define i64 @fold_xor_zext_sandwich(i1 %a) {
 ; CHECK-LABEL: @fold_xor_zext_sandwich(
-; CHECK-NEXT:    [[ZEXT1:%.*]] = zext i1 %a to i32
-; CHECK-NEXT:    [[XOR:%.*]] = xor i32 [[ZEXT1]], 1
-; CHECK-NEXT:    [[ZEXT2:%.*]] = zext i32 [[XOR]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i1 %a, true
+; CHECK-NEXT:    [[ZEXT2:%.*]] = zext i1 [[TMP1]] to i64
 ; CHECK-NEXT:    ret i64 [[ZEXT2]]
 ;
   %zext1 = zext i1 %a to i32
   %xor = xor i32 %zext1, 1
   %zext2 = zext i32 %xor to i64
   ret i64 %zext2
 }
 
 define <2 x i64> @fold_xor_zext_sandwich_vec(<2 x i1> %a) {
 ; CHECK-LABEL: @fold_xor_zext_sandwich_vec(
-; CHECK-NEXT:    [[ZEXT1:%.*]] = zext <2 x i1> %a to <2 x i64>
-; CHECK-NEXT:    [[XOR:%.*]] = xor <2 x i64> [[ZEXT1]], <i64 1, i64 1>
-; CHECK-NEXT:    ret <2 x i64> [[XOR]]
+; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i1> %a, <i1 true, i1 true>
+; CHECK-NEXT:    [[ZEXT2:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[ZEXT2]]
 ;
   %zext1 = zext <2 x i1> %a to <2 x i32>
   %xor = xor <2 x i32> %zext1, <i32 1, i32 1>
   %zext2 = zext <2 x i32> %xor to <2 x i64>
   ret <2 x i64> %zext2
 }