[SystemZ] Recognize Load On Condition Immediate (LOCHI/LOGHI) opportunities

[RolandF]

Summary

Add support for the z13 instructions LOCHI and LOCGHI which conditionally load immediate values. Add target instruction info hooks so that if conversion will allow predication of LHI/LGHI.

[uweigand]

Please also add test cases for the *assembler* for the new instructions (in test/MC/SystemZ/insn-good-z13.s, as well as checks for invalid operands in insn-bad-z13.s, and checks for missing feature in insn-bad-zEC12.s).

Otherwise, this looks all good to me, thanks!

[RolandF]

Added assembler tests.

[uweigand]

LGTM, thanks!

lib/Target/SystemZ/SystemZInstrFormats.td

class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
                    RegisterOperand cls2>
   : InstRRF<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$valid, cond4:$R3),
             mnemonic#"r$R3\t$R1, $R2", []>,
     Requires<[FeatureLoadStoreOnCond]> {
   let CCMaskLast = 1;
   let R4 = 0;
 }
 
+class CondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
+                   Immediate imm>
+  : InstRIEd<opcode, (outs cls:$R1),
+                     (ins imm:$I2, cond4:$valid, cond4:$R3),
+             mnemonic#"$R3\t$R1, $I2", []>,
+    Requires<[FeatureLoadStoreOnCond2]> {
+  let CCMaskLast = 1;
+}
+
 // Like CondUnaryRRF, but used for the raw assembly form.  The condition-code
 // mask is the third operand rather than being part of the mnemonic.
 class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
                       RegisterOperand cls2>
   : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, imm32zx4:$R3),
             mnemonic#"r\t$R1, $R2, $R3", []>,
     Requires<[FeatureLoadStoreOnCond]> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let R4 = 0;
 }
 
+class AsmCondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
+                   Immediate imm>
+  : InstRIEd<opcode, (outs cls:$R1),
+                     (ins cls:$R1src, imm:$I2, imm32zx4:$R3),
+             mnemonic#"\t$R1, $I2, $R3", []>,
+    Requires<[FeatureLoadStoreOnCond2]> {
+  let Constraints = "$R1 = $R1src";
+  let DisableEncoding = "$R1src";
+}
+
 // Like CondUnaryRRF, but with a fixed CC mask.
 class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
                         RegisterOperand cls2, bits<4> ccmask>
   : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
             mnemonic#"\t$R1, $R2", []>,
     Requires<[FeatureLoadStoreOnCond]> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let R3 = ccmask;
   let R4 = 0;
 }
 
+class FixedCondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
+                   Immediate imm, bits<4> ccmask>
+  : InstRIEd<opcode, (outs cls:$R1),
+                     (ins cls:$R1src, imm:$I2),
+             mnemonic#"\t$R1, $I2", []>,
+    Requires<[FeatureLoadStoreOnCond2]> {
+  let Constraints = "$R1 = $R1src";
+  let DisableEncoding = "$R1src";
+  let R3 = ccmask;
+}
+
 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
               RegisterOperand cls, Immediate imm>
   : InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
            mnemonic#"\t$R1, $I2",
            [(set cls:$R1, (operator imm:$I2))]>;
 
 class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
                RegisterOperand cls, Immediate imm>

lib/Target/SystemZ/SystemZInstrInfo.cpp

 static unsigned getConditionalMove(unsigned Opcode) {
   switch (Opcode) {
   case SystemZ::LR:  return SystemZ::LOCR;
   case SystemZ::LGR: return SystemZ::LOCGR;
   default:           return 0;
   }
 }
 
+static unsigned getConditionalLoadImmediate(unsigned Opcode) {
+  switch (Opcode) {
+  case SystemZ::LHI:  return SystemZ::LOCHI;
+  case SystemZ::LGHI: return SystemZ::LOCGHI;
+  default:           return 0;
+  }
+}
+
 bool SystemZInstrInfo::isPredicable(MachineInstr &MI) const {
   unsigned Opcode = MI.getOpcode();
   if (STI.hasLoadStoreOnCond() && getConditionalMove(Opcode))
     return true;
+  if (STI.hasLoadStoreOnCond2() && getConditionalLoadImmediate(Opcode))
+    return true;
   if (Opcode == SystemZ::Return ||
       Opcode == SystemZ::Trap ||
       Opcode == SystemZ::CallJG ||
       Opcode == SystemZ::CallBR)
     return true;
   return false;
 }
 
if (unsigned CondOpcode = getConditionalMove(Opcode)) {
       MI.setDesc(get(CondOpcode));
       MachineInstrBuilder(*MI.getParent()->getParent(), MI)
           .addImm(CCValid)
           .addImm(CCMask)
           .addReg(SystemZ::CC, RegState::Implicit);
       return true;
     }
   }
+  if (STI.hasLoadStoreOnCond2()) {
+    if (unsigned CondOpcode = getConditionalLoadImmediate(Opcode)) {
+      MI.setDesc(get(CondOpcode));
+      MachineInstrBuilder(*MI.getParent()->getParent(), MI)
+          .addImm(CCValid)
+          .addImm(CCMask)
+          .addReg(SystemZ::CC, RegState::Implicit);
+      return true;
+    }
+  }
   if (Opcode == SystemZ::Trap) {
     MI.setDesc(get(SystemZ::CondTrap));
     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
       .addImm(CCValid).addImm(CCMask)
       .addReg(SystemZ::CC, RegState::Implicit);
     return true;
   }
   if (Opcode == SystemZ::Return) {

lib/Target/SystemZ/SystemZInstrInfo.td

 multiclass CondExtendedMnemonicA<bits<4> ccmask, string name> {
   let isBranch = 1, isTerminator = 1, R1 = ccmask in {
     def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
                    "j"##name##"\t$I2", []>;
     def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
                      "jg"##name##"\t$I2", []>;
     def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), "b"##name##"r\t$R2", []>;
   }
-  def LOCR  : FixedCondUnaryRRF<"locr"##name,  0xB9F2, GR32, GR32, ccmask>;
-  def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
-  def LOC   : FixedCondUnaryRSY<"loc"##name,   0xEBF2, GR32, ccmask, 4>;
-  def LOCG  : FixedCondUnaryRSY<"locg"##name,  0xEBE2, GR64, ccmask, 8>;
-  def STOC  : FixedCondStoreRSY<"stoc"##name,  0xEBF3, GR32, ccmask, 4>;
-  def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
+  def LOCR  : FixedCondUnaryRRF<"locr"##name,   0xB9F2, GR32, GR32, ccmask>;
+  def LOCGR : FixedCondUnaryRRF<"locgr"##name,  0xB9E2, GR64, GR64, ccmask>;
+  def LOCHI : FixedCondUnaryRIE<"lochi"##name,  0xEC42, GR64, imm32sx16,
+                                ccmask>;
+  def LOCGHI: FixedCondUnaryRIE<"locghi"##name, 0xEC46, GR64, imm64sx16,
+                                ccmask>;
+  def LOC   : FixedCondUnaryRSY<"loc"##name,    0xEBF2, GR32, ccmask, 4>;
+  def LOCG  : FixedCondUnaryRSY<"locg"##name,   0xEBE2, GR64, ccmask, 8>;
+  def STOC  : FixedCondStoreRSY<"stoc"##name,   0xEBF3, GR32, ccmask, 4>;
+  def STOCG : FixedCondStoreRSY<"stocg"##name,  0xEBE3, GR64, ccmask, 8>;
 }
 
 multiclass CondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
   : CondExtendedMnemonicA<ccmask, name1> {
   let isAsmParserOnly = 1 in
     defm Alt : CondExtendedMnemonicA<ccmask, name2>;
 }
 

 let isCodeGenOnly = 1, Uses = [CC] in {
   def LOCR  : CondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
   def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
 }
 let Uses = [CC] in {
   def AsmLOCR  : AsmCondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
   def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
 }
+let isCodeGenOnly = 1, Uses = [CC] in {
+  def LOCHI  : CondUnaryRIE<"lochi",  0xEC42, GR32, imm32sx16>;
+  def LOCGHI : CondUnaryRIE<"locghi", 0xEC46, GR64, imm64sx16>;
+}
+let Uses = [CC] in {
+  def AsmLOCHI  : AsmCondUnaryRIE<"lochi",  0xEC42, GR32, imm32sx16>;
+  def AsmLOCGHI : AsmCondUnaryRIE<"locghi", 0xEC46, GR64, imm64sx16>;
+}
 
 // Immediate moves.
 let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
     isReMaterializable = 1 in {
   // 16-bit sign-extended immediates.  LHIMux expands to LHI or IIHF,
   // deopending on the choice of register.
   def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>,
                Requires<[FeatureHighWord]>;

lib/Target/SystemZ/SystemZProcessors.td

def FeatureDistinctOps : SystemZFeature<
   "Assume that the distinct-operands facility is installed"
 >;
 
 def FeatureLoadStoreOnCond : SystemZFeature<
   "load-store-on-cond", "LoadStoreOnCond",
   "Assume that the load/store-on-condition facility is installed"
 >;
 
+def FeatureLoadStoreOnCond2 : SystemZFeature<
+  "load-store-on-cond-2", "LoadStoreOnCond2",
+  "Assume that the load/store-on-condition facility 2 is installed"
+>;
+
 def FeatureHighWord : SystemZFeature<
   "high-word", "HighWord",
   "Assume that the high-word facility is installed"
 >;
 
 def FeatureFPExtension : SystemZFeature<
   "fp-extension", "FPExtension",
   "Assume that the floating-point extension facility is installed"
def : Processor<"zEC12", NoItineraries,
                  FeatureMiscellaneousExtensions,
                  FeatureTransactionalExecution, FeatureProcessorAssist]>;
 def : Processor<"z13", NoItineraries,
                 [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
                  FeatureFPExtension, FeaturePopulationCount,
                  FeatureFastSerialization, FeatureInterlockedAccess1,
                  FeatureMiscellaneousExtensions,
                  FeatureTransactionalExecution, FeatureProcessorAssist,
-                 FeatureVector]>;
+                 FeatureVector, FeatureLoadStoreOnCond2]>;

lib/Target/SystemZ/SystemZSubtarget.h

protected:
   bool HasFPExtension;
   bool HasPopulationCount;
   bool HasFastSerialization;
   bool HasInterlockedAccess1;
   bool HasMiscellaneousExtensions;
   bool HasTransactionalExecution;
   bool HasProcessorAssist;
   bool HasVector;
+  bool HasLoadStoreOnCond2;
 
 private:
   Triple TargetTriple;
   SystemZInstrInfo InstrInfo;
   SystemZTargetLowering TLInfo;
   SystemZSelectionDAGInfo TSInfo;
   SystemZFrameLowering FrameLowering;
 
public:
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
   // Return true if the target has the distinct-operands facility.
   bool hasDistinctOps() const { return HasDistinctOps; }
 
   // Return true if the target has the load/store-on-condition facility.
   bool hasLoadStoreOnCond() const { return HasLoadStoreOnCond; }
 
+  // Return true if the target has the load/store-on-condition facility 2.
+  bool hasLoadStoreOnCond2() const { return HasLoadStoreOnCond2; }
+
   // Return true if the target has the high-word facility.
   bool hasHighWord() const { return HasHighWord; }
 
   // Return true if the target has the floating-point extension facility.
   bool hasFPExtension() const { return HasFPExtension; }
 
   // Return true if the target has the population-count facility.
   bool hasPopulationCount() const { return HasPopulationCount; }

lib/Target/SystemZ/SystemZSubtarget.cpp

 SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
                                    const std::string &FS,
                                    const TargetMachine &TM)
     : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
       HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
       HasPopulationCount(false), HasFastSerialization(false),
       HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
       HasTransactionalExecution(false), HasProcessorAssist(false),
-      HasVector(false), TargetTriple(TT),
+      HasVector(false), HasLoadStoreOnCond2(false), TargetTriple(TT),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
       TSInfo(), FrameLowering() {}
 
 bool SystemZSubtarget::isPC32DBLSymbol(const GlobalValue *GV,
                                        CodeModel::Model CM) const {
   // PC32DBL accesses require the low bit to be clear.  Note that a zero
   // value selects the default alignment and is therefore OK.
   if (GV->getAlignment() == 1)

test/CodeGen/SystemZ/cond-li.ll

+; Test LOCHI/LOCGHI
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; CHECK-LABEL: bar1:
+; CHECK: lhi [[REG:%r[0-5]]], 42
+; CHECK: chi %r2, 0
+; CHECK: lochie [[REG]], 0
+define signext i32 @bar1(i32 signext %x) {
+  %cmp = icmp ne i32 %x, 0
+  %.x = select i1 %cmp, i32 42, i32 0
+  ret i32 %.x
+}
+
+; CHECK-LABEL: bar2:
+; CHECK: ltgr [[REG:%r[0-5]]], %r2
+; CHECK: lghi %r2, 42
+; CHECK: locghie %r2, 0
+define signext i64 @bar2(i64 signext %x) {
+  %cmp = icmp ne i64 %x, 0
+  %.x = select i1 %cmp, i64 42, i64 0
+  ret i64 %.x
+}

test/MC/Disassembler/SystemZ/insns-z13.txt

 #CHECK: wledb   %f0, %f0, 0, 0
 0xe7 0x00 0x00 0x08 0x30 0xc5
 
 #CHECK: wledb   %v19, %f14, 4, 10
 0xe7 0x3e 0x00 0xac 0x38 0xc5
 
 #CHECK: wledb   %v31, %v31, 7, 15
 0xe7 0xff 0x00 0xff 0x3c 0xc5
+
+#CHECK: lochi %r11, 42, 0
+0xec 0xb0 0x00 0x2a 0x00 0x42
+
+#CHECK: lochio %r11, 42
+0xec 0xb1 0x00 0x2a 0x00 0x42
+
+#CHECK: lochih %r11, 42
+0xec 0xb2 0x00 0x2a 0x00 0x42
+
+#CHECK: lochinle %r11, 42
+0xec 0xb3 0x00 0x2a 0x00 0x42
+
+#CHECK: lochil %r11, -1
+0xec 0xb4 0xff 0xff 0x00 0x42
+
+#CHECK: lochinhe %r11, 42
+0xec 0xb5 0x00 0x2a 0x00 0x42
+
+#CHECK: lochilh %r11, -1
+0xec 0xb6 0xff 0xff 0x00 0x42
+
+#CHECK: lochine %r11, 0
+0xec 0xb7 0x00 0x00 0x00 0x42
+
+#CHECK: lochie %r11, 0
+0xec 0xb8 0x00 0x00 0x00 0x42
+
+#CHECK: lochinlh %r11, 42
+0xec 0xb9 0x00 0x2a 0x00 0x42
+
+#CHECK: lochihe %r11, 255
+0xec 0xba 0x00 0xff 0x00 0x42
+
+#CHECK: lochinl %r11, 255
+0xec 0xbb 0x00 0xff 0x00 0x42
+
+#CHECK: lochile %r11, 32767
+0xec 0xbc 0x7f 0xff 0x00 0x42
+
+#CHECK: lochinh %r11, 32767
+0xec 0xbd 0x7f 0xff 0x00 0x42
+
+#CHECK: lochino %r11, 32512
+0xec 0xbe 0x7f 0x00 0x00 0x42
+
+#CHECK: lochi %r11, 32512, 15
+0xec 0xbf 0x7f 0x00 0x00 0x42
+
+#CHECK: locghi %r11, 42, 0
+0xec 0xb0 0x00 0x2a 0x00 0x46
+
+#CHECK: locghio %r11, 42
+0xec 0xb1 0x00 0x2a 0x00 0x46
+
+#CHECK: locghih %r11, 42
+0xec 0xb2 0x00 0x2a 0x00 0x46
+
+#CHECK: locghinle %r11, 42
+0xec 0xb3 0x00 0x2a 0x00 0x46
+
+#CHECK: locghil %r11, -1
+0xec 0xb4 0xff 0xff 0x00 0x46
+
+#CHECK: locghinhe %r11, 42
+0xec 0xb5 0x00 0x2a 0x00 0x46
+
+#CHECK: locghilh %r11, -1
+0xec 0xb6 0xff 0xff 0x00 0x46
+
+#CHECK: locghine %r11, 0
+0xec 0xb7 0x00 0x00 0x00 0x46
+
+#CHECK: locghie %r11, 0
+0xec 0xb8 0x00 0x00 0x00 0x46
+
+#CHECK: locghinlh %r11, 42
+0xec 0xb9 0x00 0x2a 0x00 0x46
+
+#CHECK: locghihe %r11, 255
+0xec 0xba 0x00 0xff 0x00 0x46
+
+#CHECK: locghinl %r11, 255
+0xec 0xbb 0x00 0xff 0x00 0x46
+
+#CHECK: locghile  %r11, 32767
+0xec 0xbc 0x7f 0xff 0x00 0x46
+
+#CHECK: locghinh %r11, 32767
+0xec 0xbd 0x7f 0xff 0x00 0x46
+
+#CHECK: locghino %r11, 32512
+0xec 0xbe 0x7f 0x00 0x00 0x46
+
+#CHECK: locghi %r11, 32512, 15
+0xec 0xbf 0x7f 0x00 0x00 0x46