fix ds_write_src2 encoding (bz26027)

[vpykhtin]

Summary

• The instruction has different opcode (fixed).

• The instruction actually does ds[A] = ds[B] so no data operands are required, only address operand.

See bz26027.

[• tstellarAMD]

LGTM.

[artem.tamazov]

Add test for _b64.

lib/Target/AMDGPU/SIInstrInfo.td

def "" : DS_Pseudo <opName, outs, ins, []>,
            AtomicNoRet<opName, 0>;
 
   let data1 = 0, vdst = 0 in {
     def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
     def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
   }
 }
 
+multiclass DS_1A0D_Off8_NORET <bits<8> op, string opName,
+  dag outs = (outs),
+  dag ins = (ins VGPR_32:$addr,
+              offset0:$offset0, offset1:$offset1, gds:$gds),
+  string asm = opName#" $addr $offset0"#"$offset1$gds"> {
+
+  def "" : DS_Pseudo <opName, outs, ins, []>;
+
+  let data0 = 0, data1 = 0, vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
+    def _si : DS_Real_si <op, opName, outs, ins, asm>;
+    def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
+  }
+}
+
 multiclass DS_1A2D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
   dag outs = (outs),
   dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
               offset0:$offset0, offset1:$offset1, gds:$gds),
   string asm = opName#" $addr, $data0, $data1$offset0$offset1$gds"> {
 
   def "" : DS_Pseudo <opName, outs, ins, []>;
 

lib/Target/AMDGPU/SIInstructions.td

 defm DS_DEC_SRC2_U32 : DS_1A <0x84, "ds_dec_src2_u32">;
 defm DS_MIN_SRC2_I32 : DS_1A <0x85, "ds_min_src2_i32">;
 defm DS_MAX_SRC2_I32 : DS_1A <0x86, "ds_max_src2_i32">;
 defm DS_MIN_SRC2_U32 : DS_1A <0x87, "ds_min_src2_u32">;
 defm DS_MAX_SRC2_U32 : DS_1A <0x88, "ds_max_src2_u32">;
 defm DS_AND_SRC2_B32 : DS_1A <0x89, "ds_and_src_b32">;
 defm DS_OR_SRC2_B32 : DS_1A <0x8a, "ds_or_src2_b32">;
 defm DS_XOR_SRC2_B32 : DS_1A <0x8b, "ds_xor_src2_b32">;
-defm DS_WRITE_SRC2_B32 : DS_1A <0x8c, "ds_write_src2_b32">;
+defm DS_WRITE_SRC2_B32 : DS_1A0D_Off8_NORET <0x8d, "ds_write_src2_b32">;
 
 defm DS_MIN_SRC2_F32 : DS_1A <0x92, "ds_min_src2_f32">;
 defm DS_MAX_SRC2_F32 : DS_1A <0x93, "ds_max_src2_f32">;
 
 defm DS_ADD_SRC2_U64 : DS_1A <0xc0, "ds_add_src2_u64">;
 defm DS_SUB_SRC2_U64 : DS_1A <0xc1, "ds_sub_src2_u64">;
 defm DS_RSUB_SRC2_U64 : DS_1A <0xc2, "ds_rsub_src2_u64">;
 defm DS_INC_SRC2_U64 : DS_1A <0xc3, "ds_inc_src2_u64">;
 defm DS_DEC_SRC2_U64 : DS_1A <0xc4, "ds_dec_src2_u64">;
 defm DS_MIN_SRC2_I64 : DS_1A <0xc5, "ds_min_src2_i64">;
 defm DS_MAX_SRC2_I64 : DS_1A <0xc6, "ds_max_src2_i64">;
 defm DS_MIN_SRC2_U64 : DS_1A <0xc7, "ds_min_src2_u64">;
 defm DS_MAX_SRC2_U64 : DS_1A <0xc8, "ds_max_src2_u64">;
 defm DS_AND_SRC2_B64 : DS_1A <0xc9, "ds_and_src2_b64">;
 defm DS_OR_SRC2_B64 : DS_1A <0xca, "ds_or_src2_b64">;
 defm DS_XOR_SRC2_B64 : DS_1A <0xcb, "ds_xor_src2_b64">;
-defm DS_WRITE_SRC2_B64 : DS_1A <0xcc, "ds_write_src2_b64">;
+defm DS_WRITE_SRC2_B64 : DS_1A0D_Off8_NORET <0xcd, "ds_write_src2_b64">;
 
 defm DS_MIN_SRC2_F64 : DS_1A <0xd2, "ds_min_src2_f64">;
 defm DS_MAX_SRC2_F64 : DS_1A <0xd3, "ds_max_src2_f64">;
 
 //===----------------------------------------------------------------------===//
 // MUBUF Instructions
 //===----------------------------------------------------------------------===//
 

test/MC/AMDGPU/ds.s

 // RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
 // RUN: llvm-mc -arch=amdgcn -mcpu=SI  -show-encoding %s | FileCheck %s --check-prefix=SICI
 // RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
 
 //===----------------------------------------------------------------------===//
 // Checks for 16-bit Offsets
 //===----------------------------------------------------------------------===//
 
 ds_add_u32 v2, v4 offset:16
 // SICI: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
 // VI:   ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
 
 //===----------------------------------------------------------------------===//
 // Checks for 2 8-bit Offsets
 //===----------------------------------------------------------------------===//
 
+ds_write_src2_b32 v2 offset0:4 offset1:8
+// SICI: ds_write_src2_b32 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x34,0xda,0x02,0x00,0x00,0x00]
+// VI:   ds_write_src2_b32 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x1a,0xd9,0x02,0x00,0x00,0x00]
+
 ds_write2_b32 v2, v4, v6 offset0:4
 // SICI: ds_write2_b32 v2, v4, v6 offset0:4 ; encoding: [0x04,0x00,0x38,0xd8,0x02,0x04,0x06,0x00]
 // VI:   ds_write2_b32 v2, v4, v6 offset0:4 ; encoding: [0x04,0x00,0x1c,0xd8,0x02,0x04,0x06,0x00]
 
 ds_write2_b32 v2, v4, v6 offset0:4 offset1:8
 // SICI: ds_write2_b32 v2, v4, v6 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x38,0xd8,0x02,0x04,0x06,0x00]
 // VI:   ds_write2_b32 v2, v4, v6 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x1c,0xd8,0x02,0x04,0x06,0x00]