AMDGPU/SI: Don't use reserved VGPRs for SGPR spilling

[• tstellarAMD]

Summary

We were using reserved VGPRs for SGPR spilling and this was causing
some programs with a workgroup size of 1024 to use more than 64
registers, which is illegal.

[arsenm]

lib/Target/AMDGPU/SIRegisterInfo.cpp

952–954 ↗

(On Diff #62820)

Instead of testing getReservedRegs you should check MRI.isAllocatable

[mareko]

FYI, This is a high priority bug. It prevents DiRT Showdown from working. Phoronix can't test the game due to that.

[• tstellarAMD]

Use MRI.isAllocatble()

[nhaehnle]

LGTM except for one comment.

lib/Target/AMDGPU/SIRegisterInfo.cpp

965 ↗

(On Diff #64486)

Reserved is unused now.

[FireBurn]

I think this fixed the issue I was seeing running BioShock at Ultra settings at 4K resolutions on my M395X

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp

unsigned SIInstrInfo::calculateLDSSpillAddress(
   unsigned WavefrontSize = ST.getWavefrontSize();
 
   unsigned TIDReg = MFI->getTIDReg();
   if (!MFI->hasCalculatedTID()) {
     MachineBasicBlock &Entry = MBB.getParent()->front();
     MachineBasicBlock::iterator Insert = Entry.front();
     DebugLoc DL = Insert->getDebugLoc();
 
-    TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
+    TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass,
+                                   *MF);
     if (TIDReg == AMDGPU::NoRegister)
       return TIDReg;
 
     if (!AMDGPU::isShader(MF->getFunction()->getCallingConv()) &&
         WorkGroupSize > WavefrontSize) {
 
       unsigned TIDIGXReg
         = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_X);

llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg (
 
   unsigned LaneVGPRIdx = Offset / (64 * 4);
   unsigned Lane = (Offset / 4) % 64;
 
   struct SpilledReg Spill;
   Spill.Lane = Lane;
 
   if (!LaneVGPRs.count(LaneVGPRIdx)) {
-    unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
+    unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass,
+                                                *MF);
 
     if (LaneVGPR == AMDGPU::NoRegister)
       // We have no VGPRs left for spilling SGPRs.
       return Spill;
 
     LaneVGPRs[LaneVGPRIdx] = LaneVGPR;
 
     // Add this register as live-in to all blocks to avoid machine verifer

llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h

public:
   ///        concurrent waves.
   unsigned getNumVGPRsAllowed(unsigned WaveCount) const;
 
   /// \brief Give the maximum number of SGPRs that can be used by \p WaveCount
   ///        concurrent waves.
   unsigned getNumSGPRsAllowed(const SISubtarget &ST, unsigned WaveCount) const;
 
   unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
-                              const TargetRegisterClass *RC) const;
+                              const TargetRegisterClass *RC,
+                              const MachineFunction &MF) const;
 
   unsigned getSGPR32PressureSet() const { return SGPR32SetID; };
   unsigned getVGPR32PressureSet() const { return VGPR32SetID; };
 
   bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
 
 private:
   void buildScratchLoadStore(MachineBasicBlock::iterator MI,

llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp

case SIRegisterInfo::WORKITEM_ID_Z:
     return AMDGPU::VGPR2;
   }
   llvm_unreachable("unexpected preloaded value type");
 }
 
 /// \brief Returns a register that is not used at any point in the function.
 ///        If all registers are used, then this function will return
 //         AMDGPU::NoRegister.
-unsigned SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
-                                           const TargetRegisterClass *RC) const {
+unsigned
+SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
+                                   const TargetRegisterClass *RC,
+                                   const MachineFunction &MF) const {
+
   for (unsigned Reg : *RC)
-    if (!MRI.isPhysRegUsed(Reg))
+    if (MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg))
       return Reg;
   return AMDGPU::NoRegister;
 }
 
 unsigned SIRegisterInfo::getNumVGPRsAllowed(unsigned WaveCount) const {
   switch(WaveCount) {
     case 10: return 24;
     case 9:  return 28;