[Sparc] Leon errata fixes passes.

[lero_chris]

Summary

Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor.

The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these.

Note: Running clang-format has changed a few other lines too, unrelated to the implemented errata fixes. These have been left in as this keeps the code formatting consistent.

[jacob_hansen]

Can't seem to find tests for the following passes:

FlushCacheLineSWAP
IgnoreZeroFlag
FixCALL

llvm/lib/Target/Sparc/LeonFeatures.td

18 ↗

(On Diff #62632)

Is this feature definition needed/used anywhere? I think the previously defined sofware floating point definition in Sparc.td is enough.

46 ↗

(On Diff #62632)

these requirement comments should probably be removed (here as well as in the descriptions).

llvm/lib/Target/Sparc/LeonPasses.cpp

654 ↗

(On Diff #62632)

Remove outcommented code.

714 ↗

(On Diff #62632)

would it make sense for the compiler to output a warning when this pass is successfully removing the call? The developer may want to know that the rounding mode change is not being executed correctly.

llvm/test/CodeGen/SPARC/LeonPreventRoundChangeUT.ll

3 ↗

(On Diff #62632)

is this check correct? Shouldn't it rather check that there is no call to fesetround ?

[lero_chris]

Update to address change recommended by comments. Small formatting changes. Missing unit tests added.

[dcederman]

lib/Target/Sparc/LeonFeatures.td

65–68

As jacob_hansen commented, this should only be a warning. It is not a good idea to remove valid function calls without notifying the user.

81–85

Flushing the cache is not a valid workaround for this errata, so this feature is not needed and will only decrease performance.

lib/Target/Sparc/LeonPasses.h

187

LBR35 is not the official name of the errata or errata fix, it should be removed to avoid confusion.

lib/Target/Sparc/Sparc.td

144

UMAC/SMAC is not available on ut699, gr712rc, or gr740.

lib/Target/Sparc/SparcISelLowering.cpp

1417–1419 ↗

(On Diff #63195)

This code has been commented out.

3100 ↗

(On Diff #63195)

This does not seem related to the errata fixes.

[lero_chris]

Further updates to address some review comments.

[jyknight]

I see you've already committed this in the time it took me to write down comments this morning. Please revert, and reopen the review. It seems to me that there are significant issues here. Some of those also present in code in LeonPasses.cpp that already was committed.

Also:

While it's not a big deal in this case, please don't do a file-wide clang-format in the same change as actual changes. You should be doing "git clang-format" or "clang-format-diff" to only format the lines you're modifying. (If the file is really egregiously ill-formatted, you can also run clang-format on the unmodified file, and commit that first).

lib/Target/Sparc/LeonFeatures.td

65–68

This doesn't appear to have been addressed.

81–85

This doesn't appear to have been addressed.

lib/Target/Sparc/LeonPasses.cpp

231–232

All of the isInlineAsm branches -- new and old -- seem wrong.

Testing instructions by looking at the prefix of the asm string can't possibly work properly. E.g., it's completely wrong if there are multiple instructions in an inline asm string.

One of two things makes sense. Either:
a) these fixes are only intended to be done on compiler-generated code. If so just remove the isInlineAsm clauses.

b) it's supposed to be done at translation of asm into object file. In which case, it should be done for an actual assembly input file too and these transforms are misplaced here.

I don't know myself how to introduce a transform at the asm level; there doesn't seem to be an obvious way to do it. Please ask for advice on the mailing list if that's what you need to do.

lib/Target/Sparc/SparcISelLowering.cpp

1642 ↗

(On Diff #63215)

This should actually have been 32. 64bit atomic instructions are not supported on leon. Also, unrelated to this change.

llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp

3380 ↗

(On Diff #63234)

Unrelated change.

3458 ↗

(On Diff #63234)

Unrelated change.

[lero_chris]

Re-opened to address latest comments.

[jyknight]

In D21960#478207, @lero_chris wrote:

Re-opened to address latest comments.

Please revert the change, too.

[lero_chris]

Addressing issues in previous review.

• Inline assembler removed.
• Non-working optimisation removed.
• Warning diagnostic generated on change of instruction behaviour for erratum fix.
• Changes to Unit tests to remove tests that work on inline assembler behaviour.
• Added (2) missing errata fixes.

[lero_chris]

Removed change to CMakeLists.txt that was relevant to a different change and inadvertently added to this review.

[dcederman]

I noticed that some of the files have been marked as executable. You should change that before committing anything.

lib/Target/Sparc/LeonPasses.cpp

757–762

How does this fill the data cache?

851–859

Erratas in trap handling should not be handled by the compiler, it should be done manually in each OS. Did you try to compile the trap handling code in, for example, Linux or RTEMS with this fix?

lib/Target/Sparc/LeonPasses.h

107–109

What is LBR29? Please add a description of the errata and the fix or a reference to an official document with the information.

What do you mean by application startup?

[lero_chris]

Modified some unit tests that were using inline assembler tests to work without this to reflect the non-use of inline assembler in the modified passes.

Removed "LBR" references to errata fixes as these were internal project references.

[lero_chris]

Addressing review comments.

lib/Target/Sparc/LeonFeatures.td

66–69

Warning now issued when this pass makes any changes.

82–85

Removed this pass if it does nothing.

lib/Target/Sparc/LeonPasses.cpp

231–232

All inline assembly code removed.

757–762

A cache stores recently-accessed data. To fill the cache, we need to access data big enough to fill the L1 cache of the LEON 2 FT CPU. To solve this problem, we use NOP instructions to fill a block of memory with NOP instructions. The LEON 2’s L1 data cache is 16 KB [6] and the size of the NOP instruction is 4 Bytes. Therefore, we need 4096 NOPs to entirely fill the cache. Note this will happen only once at the first call of the runOnMachineFunction() method.

851–859

Do you suggest that this pass should not be part of the compiler then? I can remove it if it fixes nothing.

lib/Target/Sparc/LeonPasses.h

107–109

Removed these internal project reference codes.

187

Removed these internal project reference codes.

lib/Target/Sparc/Sparc.td

144

Removed from feature set.

[dcederman]

Some more inline comments.

Could you please also revert the committed changes, like @jyknight asked you?

lib/Target/Sparc/LeonFeatures.td

88–90

A cache miss occurs when the data at the memory address accessed is not available in the cache. Filling the data cache with random data that will not be accessed again will not prevent cache misses, it will make them more likely.

Could you reference the document that describes the errata you are trying to provide a fix for? I looked in http://www.atmel.com/Images/doc4409.pdf but could not find a match.

lib/Target/Sparc/LeonPasses.cpp

757–762

But you are not accessing data? It is just a loop that does nothing. And if I understand the code correctly, you randomly add it to the first function you find?

851–859

You should remove it. Automatically changing assembly code in the trap handler is extremely risky.

[dcederman]

Why did you commit your changes mid-review? I'm reopening this review.

[lero_chris]

Hi Daniel. Nobody was commenting and I need to get this checked-in as I won't be around for three weeks now. You commented at *exactly* the same time as I did the check-in. Otherwise, I had addressed all the review comments.

I'll look at the comments and make any necessary changes when I am next at work.

[jyknight]

In D21960#513655, @lero_chris wrote:

Hi Daniel. Nobody was commenting and I need to get this checked-in as I won't be around for three weeks now. You commented at *exactly* the same time as I did the check-in. Otherwise, I had addressed all the review comments.

I'll look at the comments and make any necessary changes when I am next at work.

This is not OK. You have ignored two requests for a revert in a row now. I have reverted all of this in r278511.

[lero_chris]

Removed RestoreExecAddress and FillDataCache passes as these will have no effect.

[lero_chris]

In D21960#513813, @jyknight wrote:

In D21960#513655, @lero_chris wrote:

Hi Daniel. Nobody was commenting and I need to get this checked-in as I won't be around for three weeks now. You commented at *exactly* the same time as I did the check-in. Otherwise, I had addressed all the review comments.

I'll look at the comments and make any necessary changes when I am next at work.

This is not OK. You have ignored two requests for a revert in a row now. I have reverted all of this in r278511.

Sorry James. I had been addressing the comments. I hadn't realised that "revert" meant rolling back the repository changes too. SVN isn't something I use much and the language differs somewhat between source control systems.

I'll abandon this review and start a new review, albeit that this is all working and tested now.

[lero_chris]

Abandoned.

lib/Target/Sparc/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS Sparc.td)
 
 tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM SparcGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM SparcGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM SparcGenSubtargetInfo.inc -gen-subtarget)
 tablegen(LLVM SparcGenCallingConv.inc -gen-callingconv)
 add_public_tablegen_target(SparcCommonTableGen)
 
 add_llvm_target(SparcCodeGen
   DelaySlotFiller.cpp
   LeonPasses.cpp
+  LeonFloatOptimisations.cpp
   SparcAsmPrinter.cpp
   SparcInstrInfo.cpp
   SparcISelDAGToDAG.cpp
   SparcISelLowering.cpp
   SparcFrameLowering.cpp
   SparcMachineFunctionInfo.cpp
   SparcRegisterInfo.cpp
   SparcSubtarget.cpp

lib/Target/Sparc/LeonFeatures.td

def FixFSMULD : SubtargetFeature<"fixfsmuld", "FixFSMULD", "true",
                                  "LEON3 erratum fix: Do not select FSMULD">;
 
 def ReplaceFMULS
     : SubtargetFeature<"replacefmuls", "ReplaceFMULS", "true",
                        "LEON3 erratum fix: Replace FMULS instruction with a "
                        "routine using conversions/double precision operations "
                        "to replace FMULS">;
 
 def PreventRoundChange
     : SubtargetFeature<"prvntroundchange", "PreventRoundChange", "true",
                        "LEON3 erratum fix: Prevent any rounding mode change "
                        "request: use only the round-to-nearest rounding mode">;
 
 def FixAllFDIVSQRT
     : SubtargetFeature<"fixallfdivsqrt", "FixAllFDIVSQRT", "true",
                        "LEON3 erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD "
                        "instructions with NOPs and floating-point store">;
 
 def InsertNOPLoad
     : SubtargetFeature<"insertnopload", "InsertNOPLoad", "true",
                        "LEON3 erratum fix: Insert a NOP instruction after "
                        "every single-cycle load instruction when the next "
                        "instruction is another load/store instruction">;
 
-def FlushCacheLineSWAP
-    : SubtargetFeature<"flshcachelineswap", "FlushCacheLineSWAP", "true",
-                       "LEON3 erratum fix: Flush cache line containing the "
-                       "lock before performing any of the atomic instructions "
-                       "SWAP and LDSTUB">;
-
 def InsertNOPsLoadStore
     : SubtargetFeature<"insertnopsloadstore", "InsertNOPsLoadStore", "true",
                        "LEON3 erratum fix: Insert NOPs between "
                        "single-precision loads and the store, so the number of "
                        "instructions between is 4">;

lib/Target/Sparc/LeonPasses.h

public:
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
     return "FixCALL: Erratum Fix LBR26: restrict the size of the immediate "
            "operand of the CALL instruction to 20 bits";
   }
 };
 
+class LLVM_LIBRARY_VISIBILITY RestoreExecAddress : public LEONMachineFunctionPass {
+public:
+  static char ID;
+
+  RestoreExecAddress(TargetMachine &tm);
+  bool runOnMachineFunction(MachineFunction& MF) override;
+
+  const char *getPassName() const override {
+    return "RestoreExecAddress: ";
+  }
+};
+
 class LLVM_LIBRARY_VISIBILITY IgnoreZeroFlag : public LEONMachineFunctionPass {
 public:
   static char ID;
 
   IgnoreZeroFlag(TargetMachine &tm);
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
     return "IgnoreZeroFlag: Erratum Fix LBR28: do not rely on the zero bit "
            "flag on a divide overflow for SDIVCC and UDIVCC";
   }
 };
 
+class LLVM_LIBRARY_VISIBILITY FillDataCache : public LEONMachineFunctionPass {
+public:
+  static char ID;
+  static bool CacheFilled;
+
+  FillDataCache(TargetMachine &tm);
+  bool runOnMachineFunction(MachineFunction& MF) override;
+
+  const char *getPassName() const override {
+    return "FillDataCache: Erratum Fix LBR29: fill data cache with values at application startup";
+  }
+};
+
 class LLVM_LIBRARY_VISIBILITY InsertNOPDoublePrecision
     : public LEONMachineFunctionPass {
 public:
   static char ID;
 
   InsertNOPDoublePrecision(TargetMachine &tm);
   bool runOnMachineFunction(MachineFunction &MF) override;
 

 class LLVM_LIBRARY_VISIBILITY InsertNOPLoad : public LEONMachineFunctionPass {
 public:
   static char ID;
 
   InsertNOPLoad(TargetMachine &tm);
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
     return "InsertNOPLoad: insert a NOP instruction after "
            "every single-cycle load instruction when the next instruction is "
            "another load/store instruction";
   }
 };
 
-class LLVM_LIBRARY_VISIBILITY FlushCacheLineSWAP
-    : public LEONMachineFunctionPass {
-public:
-  static char ID;
-
-  FlushCacheLineSWAP(TargetMachine &tm);
-  bool runOnMachineFunction(MachineFunction &MF) override;
-
-  const char *getPassName() const override {
-    return "FlushCacheLineSWAP: Erratum Fix LBR36: flush cache line containing "
-           "the lock before performing any of the atomic instructions SWAP and "
-           "LDSTUB";
-  }
-};
-
 class LLVM_LIBRARY_VISIBILITY InsertNOPsLoadStore
     : public LEONMachineFunctionPass {
 public:
   static char ID;
 
   InsertNOPsLoadStore(TargetMachine &tm);
   bool runOnMachineFunction(MachineFunction &MF) override;
 

lib/Target/Sparc/LeonPasses.cpp

 //===----------------------------------------------------------------------===//
 
 #include "LeonPasses.h"
 #include "llvm/CodeGen/ISDOpcodes.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/LLVMContext.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
 LEONMachineFunctionPass::LEONMachineFunctionPass(TargetMachine &tm, char &ID)
     : MachineFunctionPass(ID) {}
 
 LEONMachineFunctionPass::LEONMachineFunctionPass(char &ID)
for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
     MachineBasicBlock &MBB = *MFI;
     for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
       MachineInstr &MI = *MBBI;
       unsigned Opcode = MI.getOpcode();
       if (Opcode >= SP::LDDArr && Opcode <= SP::LDrr) {
         MachineBasicBlock::iterator NMBBI = std::next(MBBI);
         BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
         Modified = true;
-      } else if (MI.isInlineAsm()) {
-        // Look for an inline ld or ldf instruction.
-        StringRef AsmString =
-            MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
-        if (AsmString.startswith_lower("ld")) {
-          MachineBasicBlock::iterator NMBBI = std::next(MBBI);
-          BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
-          Modified = true;
-        }
       }
     }
   }
 
   return Modified;
 }
 
 //*****************************************************************************
for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
       int Reg2Index = UNASSIGNED_INDEX;
       int Reg3Index = UNASSIGNED_INDEX;
 
       if (Opcode == SP::FSMULD && MI.getNumOperands() == 3) {
         // take the registers from fsmuld %f20,%f21,%f8
         Reg1Index = MI.getOperand(0).getReg();
         Reg2Index = MI.getOperand(1).getReg();
         Reg3Index = MI.getOperand(2).getReg();
-      } else if (MI.isInlineAsm()) {
-        StringRef AsmString =
-            MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
-        if (AsmString.startswith_lower("fsmuld")) {
-          // this is an inline FSMULD instruction
-
-          unsigned StartOp = InlineAsm::MIOp_FirstOperand;
-
-          // extracts the registers from the inline assembly instruction
-          for (unsigned i = StartOp, e = MI.getNumOperands(); i != e; ++i) {
-            const MachineOperand &MO = MI.getOperand(i);
-            if (MO.isReg()) {
-              if (Reg1Index == UNASSIGNED_INDEX)
-                Reg1Index = MO.getReg();
-              else if (Reg2Index == UNASSIGNED_INDEX)
-                Reg2Index = MO.getReg();
-              else if (Reg3Index == UNASSIGNED_INDEX)
-                Reg3Index = MO.getReg();
-            }
-            if (Reg3Index != UNASSIGNED_INDEX)
-              break;
-          }
-        }
       }
 
       if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX &&
           Reg3Index != UNASSIGNED_INDEX) {
         clearUsedRegisterList();
         MachineBasicBlock::iterator NMBBI = std::next(MBBI);
         // Whatever Reg3Index is hasn't been used yet, so we need to reserve it.
         markRegisterUsed(Reg3Index);
for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
       int Reg1Index = UNASSIGNED_INDEX;
       int Reg2Index = UNASSIGNED_INDEX;
       int Reg3Index = UNASSIGNED_INDEX;
 
       if (Opcode == SP::FMULS && MI.getNumOperands() == 3) {
         // take the registers from fmuls %f20,%f21,%f8
         Reg1Index = MI.getOperand(0).getReg();
         Reg2Index = MI.getOperand(1).getReg();
         Reg3Index = MI.getOperand(2).getReg();
-      } else if (MI.isInlineAsm()) {
-        StringRef AsmString =
-            MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
-        if (AsmString.startswith_lower("fmuls")) {
-          // this is an inline FMULS instruction
-          unsigned StartOp = InlineAsm::MIOp_FirstOperand;
-
-          // extracts the registers from the inline assembly instruction
-          for (unsigned i = StartOp, e = MI.getNumOperands(); i != e; ++i) {
-            const MachineOperand &MO = MI.getOperand(i);
-            if (MO.isReg()) {
-              if (Reg1Index == UNASSIGNED_INDEX)
-                Reg1Index = MO.getReg();
-              else if (Reg2Index == UNASSIGNED_INDEX)
-                Reg2Index = MO.getReg();
-              else if (Reg3Index == UNASSIGNED_INDEX)
-                Reg3Index = MO.getReg();
-            }
-            if (Reg3Index != UNASSIGNED_INDEX)
-              break;
-          }
-        }
       }
 
       if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX &&
           Reg3Index != UNASSIGNED_INDEX) {
         clearUsedRegisterList();
         MachineBasicBlock::iterator NMBBI = std::next(MBBI);
         // Whatever Reg3Index is hasn't been used yet, so we need to reserve it.
         markRegisterUsed(Reg3Index);
         const int ScratchReg1Index = getUnusedFPRegister(MF.getRegInfo());
bool FixAllFDIVSQRT::runOnMachineFunction(MachineFunction &MF) {
 
   bool Modified = false;
   for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
     MachineBasicBlock &MBB = *MFI;
     for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
       MachineInstr &MI = *MBBI;
       unsigned Opcode = MI.getOpcode();
 
-      if (MI.isInlineAsm()) {
-        StringRef AsmString =
-            MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
-        if (AsmString.startswith_lower("fsqrtd")) {
-          // this is an inline fsqrts instruction
-          Opcode = SP::FSQRTD;
-        } else if (AsmString.startswith_lower("fdivd")) {
-          // this is an inline fsqrts instruction
-          Opcode = SP::FDIVD;
-        }
-      }
-
       // Note: FDIVS and FSQRTS cannot be generated when this erratum fix is
       // switched on so we don't need to check for them here. They will
       // already have been converted to FSQRTD or FDIVD earlier in the
       // pipeline.
       if (Opcode == SP::FSQRTD || Opcode == SP::FDIVD) {
         // Insert 5 NOPs before FSQRTD,FDIVD.
         for (int InsertedCount = 0; InsertedCount < 5; InsertedCount++)
           BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));

 
 bool FixCALL::runOnMachineFunction(MachineFunction &MF) {
   bool Modified = false;
 
   for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
     MachineBasicBlock &MBB = *MFI;
     for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
       MachineInstr &MI = *MBBI;
-      MI.print(errs());
-      errs() << "\n";
 
       unsigned Opcode = MI.getOpcode();
       if (Opcode == SP::CALL || Opcode == SP::CALLrr) {
         unsigned NumOperands = MI.getNumOperands();
         for (unsigned OperandIndex = 0; OperandIndex < NumOperands;
              OperandIndex++) {
           MachineOperand &MO = MI.getOperand(OperandIndex);
           if (MO.isImm()) {
             int64_t Value = MO.getImm();
             MO.setImm(Value & 0x000fffffL);
             Modified = true;
             break;
           }
         }
-      } else if (MI.isInlineAsm()) // inline assembly immediate call
-      {
-        StringRef AsmString =
-            MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
-        if (AsmString.startswith_lower("call")) {
-          // this is an inline call instruction
-          unsigned StartOp = InlineAsm::MIOp_FirstOperand;
-
-          // extracts the registers from the inline assembly instruction
-          for (unsigned i = StartOp, e = MI.getNumOperands(); i != e; ++i) {
-            MachineOperand &MO = MI.getOperand(i);
-            if (MO.isImm()) {
-              int64_t Value = MO.getImm();
-              MO.setImm(Value & 0x000fffffL);
-              Modified = true;
-            }
-          }
-        }
       }
     }
   }
 
   return Modified;
 }
 
 //*****************************************************************************
for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
         // create wr %g0, 1, %psr
         BuildMI(MBB, NextMBBI, DL, TII.get(SP::WRPSRri))
             .addReg(SP::G0)
             .addImm(1);
 
         BuildMI(MBB, NextMBBI, DL, TII.get(SP::NOP));
 
         Modified = true;
-      } else if (MI.isInlineAsm()) {
-        StringRef AsmString =
-            MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
-        if (AsmString.startswith_lower("sdivcc") ||
-            AsmString.startswith_lower("udivcc")) {
-          // this is an inline SDIVCC or UDIVCC instruction
-
-          // split the current machine basic block - just after the
-          // sdivcc/udivcc instruction
-          // create a label that help us skip the zero flag update (of PSR -
-          // Processor Status Register)
-          // if conditions are not met
-          const BasicBlock *LLVM_BB = MBB.getBasicBlock();
-          MachineFunction::iterator It =
-              std::next(MachineFunction::iterator(MBB));
-
-          MachineBasicBlock *dneBB = MF.CreateMachineBasicBlock(LLVM_BB);
-          MF.insert(It, dneBB);
-
-          // Transfer the remainder of MBB and its successor edges to dneBB.
-          dneBB->splice(dneBB->begin(), &MBB,
-                        std::next(MachineBasicBlock::iterator(MI)), MBB.end());
-          dneBB->transferSuccessorsAndUpdatePHIs(&MBB);
-
-          MBB.addSuccessor(dneBB);
-
-          MachineBasicBlock::iterator NextMBBI = std::next(MBBI);
-
-          // bvc - branch if overflow flag not set
-          BuildMI(MBB, NextMBBI, DL, TII.get(SP::BCOND))
-              .addMBB(dneBB)
-              .addImm(SPCC::ICC_VS);
-
-          // bnz - branch if not zero
-          BuildMI(MBB, NextMBBI, DL, TII.get(SP::BCOND))
-              .addMBB(dneBB)
-              .addImm(SPCC::ICC_NE);
-
-          // use the WRPSR (Write Processor State Register) instruction to set
-          // the zeo flag to 1
-          // create wr %g0, 1, %psr
-          BuildMI(MBB, NextMBBI, DL, TII.get(SP::WRPSRri))
-              .addReg(SP::G0)
-              .addImm(1);
-
-          BuildMI(MBB, NextMBBI, DL, TII.get(SP::NOP));
-
-          Modified = true;
-        }
       }
     }
   }
 
   return Modified;
 }
 
 //*****************************************************************************
for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
     for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
       MachineInstr &MI = *MBBI;
       unsigned Opcode = MI.getOpcode();
       if (Opcode == SP::LDDFri || Opcode == SP::LDDFrr) {
         MachineBasicBlock::iterator NMBBI = std::next(MBBI);
         MachineInstr &NMI = *NMBBI;
 
         unsigned NextOpcode = NMI.getOpcode();
-        // NMI.print(errs());
         if (NextOpcode == SP::FADDD || NextOpcode == SP::FSUBD ||
             NextOpcode == SP::FMULD || NextOpcode == SP::FDIVD) {
           int RegAIndex = GetRegIndexForOperand(MI, 0);
           int RegBIndex = GetRegIndexForOperand(NMI, 0);
           int RegCIndex =
               GetRegIndexForOperand(NMI, 2); // Second source operand is index 2
           int RegDIndex =
               GetRegIndexForOperand(NMI, 1); // Destination operand is index 1
for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
       unsigned Opcode = MI.getOpcode();
       if (Opcode == SP::CALL && MI.getNumOperands() > 0) {
         MachineOperand &MO = MI.getOperand(0);
 
         if (MO.isGlobal()) {
           StringRef FuncName = MO.getGlobal()->getName();
           if (FuncName.compare_lower("fesetround") == 0) {
             MachineBasicBlock::iterator NMBBI = std::next(MBBI);
+            emitOptimizationRemark(
+                MF.getFunction()->getContext(), getPassName(), *MF.getFunction(),
+                MI.getDebugLoc(), "Warning: You are using the prvntroundchange "
+                                  "option to prevent rounding changes caused "
+                                  "by LEON errata. A call to fesetround to be "
+                                  "removed from the output.");
             MI.eraseFromParent();
             MBBI = NMBBI;
             Modified = true;
           }
         }
       }
     }
   }
 
   return Modified;
 }
 //*****************************************************************************
-//**** FlushCacheLineSWAP pass
-//*****************************************************************************
-// This pass inserts FLUSHW just before any SWAP atomic instruction.
-//
-char FlushCacheLineSWAP::ID = 0;
-
-FlushCacheLineSWAP::FlushCacheLineSWAP(TargetMachine &tm)
-    : LEONMachineFunctionPass(tm, ID) {}
-
-bool FlushCacheLineSWAP::runOnMachineFunction(MachineFunction &MF) {
-  Subtarget = &MF.getSubtarget<SparcSubtarget>();
-  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
-  DebugLoc DL = DebugLoc();
-
-  bool Modified = false;
-  for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
-    MachineBasicBlock &MBB = *MFI;
-    for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
-      MachineInstr &MI = *MBBI;
-      unsigned Opcode = MI.getOpcode();
-      if (Opcode == SP::SWAPrr || Opcode == SP::SWAPri ||
-          Opcode == SP::LDSTUBrr || Opcode == SP::LDSTUBri) {
-        // insert flush and 5 NOPs before the swap/ldstub instruction
-        BuildMI(MBB, MBBI, DL, TII.get(SP::FLUSH));
-        BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
-        BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
-        BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
-        BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
-        BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
-
-        Modified = true;
-      } else if (MI.isInlineAsm()) {
-        StringRef AsmString =
-            MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
-        if (AsmString.startswith_lower("swap") ||
-            AsmString.startswith_lower("ldstub")) {
-          // this is an inline swap or ldstub instruction
-
-          // insert flush and 5 NOPs before the swap/ldstub instruction
-          BuildMI(MBB, MBBI, DL, TII.get(SP::FLUSH));
-          BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
-          BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
-          BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
-          BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
-          BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
-
-          Modified = true;
-        }
-      }
-    }
-  }
-
-  return Modified;
-}
-
-//*****************************************************************************
 //**** InsertNOPsLoadStore pass
 //*****************************************************************************
 // This pass shall insert NOPs between floating point loads and stores when the
 // following circumstances are present [5]:
 // Pattern 1:
 // 1. single-precision load or single-precision FPOP to register %fX, where X is
 // the same register as the store being checked;
 // 2. single-precision load or single-precision FPOP to register %fY , where Y
for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
           Pattern1FirstInstruction = NULL;
         break;
       }
     }
   }
 
   return Modified;
 }
+
+
+//****************************************************************************************************************
+//**** FillDataCache pass
+//****************************************************************************************************************
+// This erratum fix inserts after the first operand a loop performing 4096 NOP
+// instructions.
+//
+// mov 0, %l0
+// mov 4096, %l1
+// loop1:
+// inc %l0
+// cmp %l0, %l1
+// ble loop1
+
+char FillDataCache::ID = 0;
+bool FillDataCache::CacheFilled = false;
+
+FillDataCache::FillDataCache(TargetMachine &tm)
+    : LEONMachineFunctionPass(tm, ID) {}
+
+bool FillDataCache::runOnMachineFunction(MachineFunction &MF) {
+  Subtarget = &MF.getSubtarget<SparcSubtarget>();
+  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
+  DebugLoc DL = DebugLoc();
+
+  unsigned int CountInstr = 0;
+
+  bool Modified = false;
+  if (!CacheFilled) {
+    for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
+
+      if (CacheFilled)
+        break;
+
+      MachineBasicBlock &MBB = *MFI;
+
+      for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
+        MachineInstr &MI = *MBBI;
+
+        CountInstr++;
+        MachineBasicBlock::iterator NextMBBI = std::next(MBBI);
+        MBBI = NextMBBI;
+
+        // insert the following sequence right after the first instruction
+        // initializing the stack pointer (sp register)
+        // or %g0, 1, %g1
+        // loop1:
+        // nop
+        // add %g1, 1, %g1
+        // cmp %g1, 4096
+        // ble  .LBB0_1
+        if (CountInstr == 1) {
+          BuildMI(MBB, NextMBBI, DL, TII.get(SP::ORrr))
+              .addReg(SP::G1)
+              .addReg(SP::G0)
+              .addImm(1);
+        } else {
+          const BasicBlock *LLVM_BB = MBB.getBasicBlock();
+          MachineBasicBlock *dneBB = MF.CreateMachineBasicBlock(LLVM_BB);
+
+          MachineFunction::iterator It =
+              std::next(MachineFunction::iterator(MBB));
+
+          MF.insert(It, dneBB);
+
+          BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
+
+          BuildMI(MBB, MBBI, DL, TII.get(SP::ADDri))
+              .addReg(SP::G1)
+              .addReg(SP::G1)
+              .addImm(1);
+
+          BuildMI(MBB, MBBI, DL, TII.get(SP::CMPri))
+              .addReg(SP::G1)
+              .addImm(4096);
+
+          BuildMI(MBB, MBBI, DL, TII.get(SP::BCOND))
+              .addMBB(dneBB)
+              .addImm(SPCC::ICC_LE);
+
+          dneBB->splice(dneBB->begin(), &MBB,
+                        std::next(MachineBasicBlock::iterator(MI)), MBB.end());
+          dneBB->transferSuccessorsAndUpdatePHIs(&MBB);
+
+          MBB.addSuccessor(dneBB);
+
+          CacheFilled = true;
+          Modified = true;
+          break;
+        }
+      }
+    }
+  }
+
+  return Modified;
+}
+
+
+//****************************************************************************************************************
+//**** RestoreExecAddress pass
+//****************************************************************************************************************
+// This erratum fix should handle user traps of FPU exceptions and restore the
+// execution address by skipping the trapped FPU instruction.
+// The algorithm:
+// find rett - return from trap
+// insert code before rett to:
+// 1. load the FSR register
+// 2. check if there is an FPU exception
+// 3. branch to old rett if there is no exception
+// 4. rett to a restored exec address
+char RestoreExecAddress::ID = 0;
+
+RestoreExecAddress::RestoreExecAddress(TargetMachine &tm)
+    : LEONMachineFunctionPass(tm, ID) {}
+
+bool RestoreExecAddress::runOnMachineFunction(MachineFunction &MF) {
+  Subtarget = &MF.getSubtarget<SparcSubtarget>();
+  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
+  DebugLoc DL = DebugLoc();
+
+  bool Modified = false;
+  for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
+    MachineBasicBlock &MBB = *MFI;
+    bool ExecAddressRestored = false;
+    for (auto NMBBI = MBB.begin(), E = MBB.end(); NMBBI != E; ++NMBBI) {
+
+      if (NMBBI != E && !ExecAddressRestored) {
+        MachineBasicBlock::iterator MBBI = std::next(NMBBI);
+        MachineInstr &MI = *MBBI;
+        unsigned Opcode = MI.getOpcode();
+
+        if (Opcode == SP::RETTrr || Opcode == SP::RETTri) {
+
+          const BasicBlock *LLVM_BB = MBB.getBasicBlock();
+
+          MachineBasicBlock *dneBB = MF.CreateMachineBasicBlock(LLVM_BB);
+
+          // gets the FSR - floating point status register;
+          // the firts 4 bits are *cexc* - current exception flags
+          BuildMI(MBB, MBBI, DL, TII.get(SP::STFSRrr)).addReg(SP::L7).addImm(0);
+
+          BuildMI(MBB, MBBI, DL, TII.get(SP::LDrr))
+              .addReg(SP::L7)
+              .addReg(SP::L7)
+              .addImm(0);
+
+          // performs a bitwise AND with b1111 to check the first 4 bits of FSR
+          // (cexc)
+          // if cexc is not zero, then it is an FPU exception
+          BuildMI(MBB, MBBI, DL, TII.get(SP::ANDri))
+              .addReg(SP::L7)
+              .addReg(SP::L7)
+              .addImm(15);
+
+          BuildMI(MBB, MBBI, DL, TII.get(SP::CMPri)).addReg(SP::L7).addImm(0);
+
+          BuildMI(MBB, MBBI, DL, TII.get(SP::BCOND))
+              .addMBB(dneBB)
+              .addImm(SPCC::ICC_E);
+          // BuildMI(&MBB, DL,
+          // TII.get(SP::BCOND)).addMBB(dneBB).addImm(SPCC::ICC_E);
+
+          BuildMI(MBB, MBBI, DL, TII.get(SP::RETTri)).addReg(SP::L2).addImm(4);
+
+          MachineFunction::iterator It =
+              std::next(MachineFunction::iterator(MBB));
+          MF.insert(It, dneBB);
+
+          // Transfer the remainder of MBB and its successor edges to dneBB.
+          dneBB->splice(dneBB->begin(), &MBB, MachineBasicBlock::iterator(MI),
+                        MBB.end());
+          dneBB->transferSuccessorsAndUpdatePHIs(&MBB);
+
+          MBB.addSuccessor(dneBB);
+
+          ExecAddressRestored = true;
+          Modified = true;
+        }
+      }
+    }
+  }
+
+  return Modified;
+}
+

lib/Target/Sparc/Sparc.td

 // LEON 3 FT generic
 def : Processor<"leon3", LEON3Itineraries, [ FeatureLeon, UMACSMACSupport ]>;
 
 // LEON 3 FT (UT699). Provides features for the UT699 processor
 // - covers all the erratum fixes for LEON3, but does not support the CASA
 // instruction.
 def : Processor<"ut699", LEON3Itineraries, [
   FeatureLeon, FixFSMULD, ReplaceFMULS, PreventRoundChange,
-  FixAllFDIVSQRT, InsertNOPLoad, FlushCacheLineSWAP, InsertNOPsLoadStore
+  FixAllFDIVSQRT, InsertNOPLoad, InsertNOPsLoadStore
 ]>;
 
 // LEON3 FT (GR712RC). Provides features for the GR712RC processor.
 // - covers all the erratum fixed for LEON3 and support for the CASA
 // instruction.
 def : Processor<"gr712rc", LEON3Itineraries,
                 [ FeatureLeon, LeonCASA ]>;
 
 // LEON 4 FT generic
 def : Processor<"leon4", LEON4Itineraries,
                 [ FeatureLeon, LeonCASA ]>;
 
 // GR740: Provides full coverage of GR740 - covers all the erratum fixes for
 // LEON3 + support to CASA + LEON 4 instruction timings
 def : Processor<"gr740", LEON4Itineraries,
                 [ FeatureLeon, LeonCASA ]> {}
 
 //===----------------------------------------------------------------------===//
 // Declare the target which we are implementing
 //===----------------------------------------------------------------------===//
 
 def SparcAsmWriter : AsmWriter {
   string AsmWriterClassName = "InstPrinter";
   int PassSubtarget = 1;
   int Variant = 0;
 }
 
 def Sparc : Target {
   // Pull in Instruction Info:
   let InstructionSet = SparcInstrInfo;
   let AssemblyParsers = [ SparcAsmParser ];
   let AssemblyWriters = [ SparcAsmWriter ];
 }

lib/Target/Sparc/SparcSubtarget.h

class SparcSubtarget : public SparcGenSubtargetInfo {
   bool ReplaceFMULS;
   bool FixAllFDIVSQRT;
   bool UseSoftFpu;
   bool PerformSDIVReplace;
   bool FixCallImmediates;
   bool IgnoreZeroFlag;
   bool InsertNOPDoublePrecision;
   bool PreventRoundChange;
-  bool FlushCacheLineSWAP;
   bool InsertNOPsLoadStore;
 
   SparcInstrInfo InstrInfo;
   SparcTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
   SparcFrameLowering FrameLowering;
 
 public:
public:
   bool performSDIVReplace() const { return PerformSDIVReplace; }
   bool fixCallImmediates() const { return FixCallImmediates; }
   bool ignoreZeroFlag() const { return IgnoreZeroFlag; }
   bool insertNOPDoublePrecision() const { return InsertNOPDoublePrecision; }
   bool fixFSMULD() const { return FixFSMULD; }
   bool replaceFMULS() const { return ReplaceFMULS; }
   bool preventRoundChange() const { return PreventRoundChange; }
   bool fixAllFDIVSQRT() const { return FixAllFDIVSQRT; }
-  bool flushCacheLineSWAP() const { return FlushCacheLineSWAP; }
   bool insertNOPsLoadStore() const { return InsertNOPsLoadStore; }
   bool insertNOPLoad() const { return InsertNOPLoad; }
 
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
   SparcSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 

lib/Target/Sparc/SparcSubtarget.cpp

SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
   FixCallImmediates = false;
   IgnoreZeroFlag = false;
   InsertNOPDoublePrecision = false;
   FixFSMULD = false;
   ReplaceFMULS = false;
   PreventRoundChange = false;
   FixAllFDIVSQRT = false;
   InsertNOPLoad = false;
-  FlushCacheLineSWAP = false;
   InsertNOPsLoadStore = false;
 
   // Determine default and user specified characteristics
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = (Is64Bit) ? "v9" : "v8";
 
   // Parse features string.

lib/Target/Sparc/SparcTargetMachine.cpp

if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT()) {
     addPass(new FixAllFDIVSQRT(getSparcTargetMachine()));
   }
   if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPsLoadStore()) {
     addPass(new InsertNOPsLoadStore(getSparcTargetMachine()));
   }
   if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad()) {
     addPass(new InsertNOPLoad(getSparcTargetMachine()));
   }
-  if (this->getSparcTargetMachine().getSubtargetImpl()->flushCacheLineSWAP()) {
-    addPass(new FlushCacheLineSWAP(getSparcTargetMachine()));
-  }
   if (this->getSparcTargetMachine()
           .getSubtargetImpl()
           ->insertNOPDoublePrecision()) {
     addPass(new InsertNOPDoublePrecision(getSparcTargetMachine()));
   }
 }
 
 void SparcV8TargetMachine::anchor() {}

test/CodeGen/SPARC/LeonFillDataCachePassUT.ll

+; RUN: llc %s -O0 -march=sparc -mcpu=leon2 -mattr=+flldatacache -o - | FileCheck %s
+; RUN: llc %s -O0 -march=sparc -mcpu=at697e -o - | FileCheck %s
+; RUN: llc %s -O0 -march=sparc -mcpu=at697f -mattr=+flldatacache -o - | FileCheck %s
+
+; CHECK-LABEL: test_filldatacache_1
+; CHECK:       or %g0, 1, %g1
+; CHECK:       nop
+; CHECK-NEXT:  add %g1, 1, %g1
+; CHECK-NEXT:  cmp %g1, 4096
+; CHECK-NEXT:  ble {{.+}}
+define zeroext i1@test_filldatacache_1(i1 zeroext %a, i1 zeroext %b) {
+  %1 = tail call zeroext i1 asm sideeffect "udivcc $0, $1, $2", "=r,r,r"(i1 zeroext %a, i1 zeroext %b)
+
+  ret i1 %1
+}
+
+
+; CHECK-LABEL: test_filldatacache_2
+; CHECK-NOT:   or %g0, 1, %g1
+; CHECK-NOT:   add %g1, 1, %g1
+; CHECK-NOT:   cmp %g1, 4096
+; CHECK-NOT:   ble {{.+}}
+define zeroext i1@test_filldatacache_2(i1 zeroext %a, i1 zeroext %b) {
+  %1 = tail call zeroext i1 asm sideeffect "sdivcc $0, $1, $2", "=r,r,r"(i1 zeroext %a, i1 zeroext %b)
+
+  ret i1 %1
+}
 No newline at end of file

test/CodeGen/SPARC/LeonFixCALLPassUT.ll

-; RUN: llc %s -O0 -march=sparc -mcpu=at697e -o - | FileCheck %s -check-prefix=FIXCALL
-; RUN: llc %s -O0 -march=sparc -mcpu=leon2 -mattr=+fixcall -o - | FileCheck %s -check-prefix=FIXCALL
-
-; RUN: llc %s -O0 -march=sparc -mcpu=at697e -mattr=-fixcall -o - | FileCheck %s -check-prefix=NO_FIXCALL
-; RUN: llc %s -O0 -march=sparc -mcpu=leon2  -o - | FileCheck %s -check-prefix=NO_FIXCALL
-
-
-; FIXCALL-LABEL:        immediate_call_test
-; FIXCALL:        call 763288
-
-; NO_FIXCALL-LABEL:     immediate_call_test
-; NO_FIXCALL:         call 2047583640
-define void @immediate_call_test() nounwind {
-entry:
-        call void asm sideeffect "call $0", "i"(i32 2047583640) nounwind
-        ret void
-}
-
-
-

test/CodeGen/SPARC/LeonInsertNOPLoadPassUT.ll

 
 ; CHECK-LABEL: ld_i32_test
 ; CHECK:       ld [%o0], %o0
 ; CHECK-NEXT:  nop
 define i32 @ld_i32_test(i32 *%p) {
   %res = load i32, i32* %p
   ret i32 %res
 }
-
-; CHECK-LABEL: ld_inlineasm_test_1
-; CHECK:       ld [%o0], %o0
-; CHECK-NEXT:  !NO_APP
-; CHECK-NEXT:  nop
-define float @ld_inlineasm_test_1(float* %a) {
-entry:
-  %res = tail call float asm sideeffect "ld [$1], $0", "=r,r"(float* %a)
-
-  ret float %res
-}
-
-; CHECK-LABEL: ld_inlineasm_test_2
-; CHECK:       ld [%o0], %o0
-; CHECK-NEXT:  !NO_APP
-; CHECK-NEXT:  nop
-define i32 @ld_inlineasm_test_2(i32* %a) {
-entry:
-  %res = tail call i32 asm sideeffect "ld [$1], $0", "=r,r"(i32* %a)
-
-  ret i32 %res
-}
 

test/CodeGen/SPARC/LeonRestExecAddrPassUT.ll

+; RUN: llc %s -O0 -march=sparc -mcpu=leon2 -mattr=+restexecaddr -o - | FileCheck %s
+; RUN: llc %s -O0 -march=sparc -mcpu=at697e -o - | FileCheck %s
+; RUN: llc %s -O0 -march=sparc -mcpu=at697f -mattr=+restexecaddr -o - | FileCheck %s
+; RUN: llc %s -O0 -march=sparc -mcpu=leon2 -o - | FileCheck %s -check-prefix=FixOff
+
+declare void @llvm.trap()
+
+; CHECK-LABEL: test_restexecaddr_1
+; CHECK:       ta 5
+; CHECK:       st %fsr, [%l7]
+; CHECK-NEXT:  ld [%l7], %l7
+; CHECK-NEXT:  and %l7, 15, %l7
+; CHECK-NEXT:  cmp %l7, 0
+; CHECK-NEXT:  be 
+; CHECK-NEXT:  rett %l2+4
+; CHECK:  rett %g0
+; FixOff-LABEL: test_restexecaddr_1
+; FixOff-NOT:   st %fsr, [%l7]
+; FixOff-NOT:   ld [%l7], %l7
+; FixOff-NOT:   and %l7, 15, %l7
+; FixOff-NOT:   cmp %l7, 0
+; FixOff-NOT:   be
+; FixOff-NOT:   rett %l2+4
+define void @test_restexecaddr_1() {
+  call void @llvm.trap()
+  call void asm sideeffect "rett %g0", ""()
+
+  ret void
+}
+
+; CHECK-LABEL: test_restexecaddr_2
+; CHECK-NOT:   st %fsr, [%l7]
+; CHECK-NOT:   ld [%l7], %l7
+; CHECK-NOT:   and %l7, 15, %l7
+; CHECK-NOT:   cmp %l7, 0
+; CHECK-NOT:   be
+; CHECK-NOT:   rett %l2+4
+define zeroext i1@test_restexecaddr_2(i1 zeroext %a, i1 zeroext %b) {
+  %1 = tail call zeroext i1 asm sideeffect "udivcc $0, $1, $2", "=r,r,r"(i1 zeroext %a, i1 zeroext %b)
+
+  ret i1 %1
+}
+
+; CHECK-LABEL: test_restexecaddr_3
+; CHECK:       ta 5
+; CHECK:       st %fsr, [%l7]
+; CHECK-NEXT:  ld [%l7], %l7
+; CHECK-NEXT:  and %l7, 15, %l7
+; CHECK-NEXT:  cmp %l7, 0
+; CHECK-NEXT:  be 
+; CHECK-NEXT:  rett %l2+4
+; CHECK:  rett %g0
+; FixOff-LABEL: test_restexecaddr_3
+; FixOff-NOT:   st %fsr, [%l7]
+; FixOff-NOT:   ld [%l7], %l7
+; FixOff-NOT:   and %l7, 15, %l7
+; FixOff-NOT:   cmp %l7, 0
+; FixOff-NOT:   be
+; FixOff-NOT:   rett %l2+4
+define void @test_restexecaddr_3() {
+  call void @llvm.trap()
+  call void asm sideeffect "rett %g0", ""()
+
+  ret void
+}
 No newline at end of file