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AVX-512: Optimization for patterns with i1 scalar type
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Authored by delena on Jul 3 2016, 5:02 AM.

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Summary

The patch removes redundant kmov instructions (not all, we still have a lot of work here) and redundant "and" instructions after "setcc".
I use "AssertZero" marker between X86ISD::SETCC node and "truncate" to eliminate extra "and $1" instruction.
I also changed zext, aext and trunc patterns in the .td file. It allows to remove extra "kmov" instruictions.

Fast ISEL mode is not supported correctly for AVX-512. ICMP/FCMP scalar instruction should return result in k-reg. It will be fixed in one of the next patches. I redirected handling of "cmp" to the DAG builder mode. (The code looks worse in one specific test case, but without this fix the new patch fails).

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rL LLVM

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delena updated this revision to Diff 62620.Jul 3 2016, 5:02 AM
delena retitled this revision from to AVX-512: Optimization for patterns with i1 scalar type.
delena updated this object.
delena set the repository for this revision to rL LLVM.
delena added a subscriber: llvm-commits.
igorb accepted this revision.Jul 4 2016, 5:32 AM
igorb edited edge metadata.

few minor comments,
LGTM

../lib/Target/X86/X86ISelLowering.cpp
15518 ↗(On Diff #62620)

This is common sequence, may be it worth to create small help function.

15551 ↗(On Diff #62620)

could you please add a few lines of comments

26618 ↗(On Diff #62620)

could you please update commnets

This revision is now accepted and ready to land.Jul 4 2016, 5:32 AM
This revision was automatically updated to reflect the committed changes.