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Differential D21929

[ARM] Correct t2UMAAL Description
ClosedPublic

Authored by samparker on Jul 1 2016, 9:03 AM.

Details

Reviewers
rengolin
Commits
rG6ca4bbb00d3b: [ARM] Refactor Thumb2 Mul and Mla instr descs
rL275979: [ARM] Refactor Thumb2 Mul and Mla instr descs
Summary

Green dragon buildbot caught an error:

http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_build/22367/

During the refactor of multiplication instructions in my previous commit, I missed updating t2UMAAL and there was no test to catch the failure.

commit r274347 was reverted so I have now updated the patch from D21549 to include the correction, plus the additional tests.

Diff Detail

Event Timeline

samparker updated this revision to Diff 62499.Jul 1 2016, 9:03 AM
samparker retitled this revision from to [ARM] Correct t2UMAAL Description.
samparker updated this object.
Herald added subscribers: rengolin, aemerson. · View Herald TranscriptJul 1 2016, 9:03 AM
t.p.northover added a subscriber: t.p.northover.Jul 1 2016, 9:28 AM

So the actual change is that we recognize the "$src = $dst" constraint? The test doesn't actually check that (and in fact seems like it would pass right now).

samparker added a comment.Jul 1 2016, 10:11 AM

well this test is just to make sure we can generate the instruction without the compiler crashing.

t.p.northover added a comment.Jul 1 2016, 10:17 AM

Sure, it's not useless, but it's not testing what's actually changing in this patch either.

samparker added a comment.Jul 1 2016, 10:25 AM

Ok, good point. So you would suggest to make another test similar to MACLongTest5?

t.p.northover added a comment.Jul 1 2016, 10:27 AM

Yep, that looks like it covers it.

samparker added a comment.Jul 1 2016, 10:28 AM

ok, cheers. revision to follow

samparker updated this object.Jul 1 2016, 12:30 PM
samparker updated this revision to Diff 62521.Jul 1 2016, 12:33 PM
samparker updated this object.
samparker added a comment.Jul 11 2016, 1:17 AM

Could someone review this please? The only change over D21549 is the test file changes and the one line change (line 2575) for the t2UMAAL description.

rengolin added a comment.Jul 11 2016, 1:41 AM

Sam, isn't this the same patch as D21549?

samparker added a comment.Jul 11 2016, 1:44 AM

Basically yes, but with a more robust test case and the correction to UMAAL which caused the buildbots to fail. The original commit was reverted so I've corrected the issues and updated the original.

rengolin added a comment.Jul 11 2016, 1:51 AM

Ah, yes. Can you add the new patch to that review as well, so we can get a diff on just what makes the test work?

samparker added a comment.Jul 11 2016, 1:52 AM

yeah, sure

samparker added a comment.Jul 14 2016, 7:25 AM

ping. i updated the original ticket.

rengolin accepted this revision.Jul 19 2016, 6:25 AM
rengolin added a reviewer: rengolin.

This looks reasonable to me, though I forgot what the breakage was in the buildbot. Tests look better, though.

lib/Target/ARM/ARMInstrThumb2.td
2575

This seems to be the only new change...

This revision is now accepted and ready to land.Jul 19 2016, 6:25 AM
Closed by commit rL275979: [ARM] Refactor Thumb2 Mul and Mla instr descs (authored by sam_parker). · Explain WhyJul 19 2016, 7:51 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
ARM/
471 lines
test/
CodeGen/
ARM/
30 lines

Diff 62521

lib/Target/ARM/ARMInstrThumb2.td

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
let Inst{19-16} = Rn; let Inst{19-16} = Rn;
let Inst{15-12} = Ra; let Inst{15-12} = Ra;
let Inst{11-8} = Rd; let Inst{11-8} = Rd;
let Inst{3-0} = Rm; let Inst{3-0} = Rm;
} }
class T2MulLong<bits<3> opc22_20, bits<4> opc7_4, class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
dag oops, dag iops, InstrItinClass itin, string opc, list<dag> pattern>
string opc, string asm, list<dag> pattern> : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
: T2I<oops, iops, itin, opc, asm, pattern> { opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern> {
bits<4> RdLo; bits<4> RdLo;
bits<4> RdHi; bits<4> RdHi;
bits<4> Rn; bits<4> Rn;
bits<4> Rm; bits<4> Rm;
let Inst{31-23} = 0b111110111; let Inst{31-23} = 0b111110111;
let Inst{22-20} = opc22_20; let Inst{22-20} = opc22_20;
let Inst{19-16} = Rn; let Inst{19-16} = Rn;
let Inst{15-12} = RdLo; let Inst{15-12} = RdLo;
let Inst{11-8} = RdHi; let Inst{11-8} = RdHi;
let Inst{7-4} = opc7_4; let Inst{7-4} = opc7_4;
let Inst{3-0} = Rm; let Inst{3-0} = Rm;
} }
class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, string opc>
dag oops, dag iops, InstrItinClass itin, : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
string opc, string asm, list<dag> pattern> (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
: T2I<oops, iops, itin, opc, asm, pattern> { opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi"> {
bits<4> RdLo; bits<4> RdLo;
bits<4> RdHi; bits<4> RdHi;
bits<4> Rn; bits<4> Rn;
bits<4> Rm; bits<4> Rm;
let Inst{31-23} = 0b111110111; let Inst{31-23} = 0b111110111;
let Inst{22-20} = opc22_20; let Inst{22-20} = opc22_20;
let Inst{19-16} = Rn; let Inst{19-16} = Rn;
▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
[(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> { [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b000; let Inst{22-20} = 0b000;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-4} = 0b0000; // Multiply let Inst{7-4} = 0b0000; // Multiply
} }
def t2MLA: T2FourReg< class T2FourRegMLA<bits<4> op7_4, string opc, list<dag> pattern>
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
"mla", "\t$Rd, $Rn, $Rm, $Ra", opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
[(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]>, Requires<[IsThumb2, UseMulOps]> {
Requires<[IsThumb2, UseMulOps]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b000; let Inst{22-20} = 0b000;
let Inst{7-4} = 0b0000; // Multiply let Inst{7-4} = op7_4;
} }
def t2MLS: T2FourReg< def t2MLA : T2FourRegMLA<0b0000, "mla",
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm),
"mls", "\t$Rd, $Rn, $Rm, $Ra", rGPR:$Ra))]>;
[(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]>, def t2MLS: T2FourRegMLA<0b0001, "mls",
Requires<[IsThumb2, UseMulOps]> { [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn,
let Inst{31-27} = 0b11111; rGPR:$Rm)))]>;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b000;
let Inst{7-4} = 0b0001; // Multiply and Subtract
}
// Extra precision multiplies with low / high results // Extra precision multiplies with low / high results
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
let isCommutable = 1 in { let isCommutable = 1 in {
def t2SMULL : T2MulLong<0b000, 0b0000, def t2SMULL : T2MulLong<0b000, 0b0000, "smull", []>;
(outs rGPR:$RdLo, rGPR:$RdHi), def t2UMULL : T2MulLong<0b010, 0b0000, "umull", []>;
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
"smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
def t2UMULL : T2MulLong<0b010, 0b0000,
(outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
"umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
} // isCommutable } // isCommutable
// Multiply + accumulate // Multiply + accumulate
def t2SMLAL : T2MlaLong<0b100, 0b0000, def t2SMLAL : T2MlaLong<0b100, 0b0000, "smlal">;
(outs rGPR:$RdLo, rGPR:$RdHi), def t2UMLAL : T2MlaLong<0b110, 0b0000, "umlal">;
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>;
rengolinUnsubmitted
Not Done
ReplyInline Actions

This seems to be the only new change...

rengolin: This seems to be the only new change...
"smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
def t2UMLAL : T2MlaLong<0b110, 0b0000,
(outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
"umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
def t2UMAAL : T2MulLong<0b110, 0b0110,
(outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
"umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
Requires<[IsThumb2, HasDSP]>;
} // hasSideEffects } // hasSideEffects
// Rounding variants of the below included for disassembly only // Rounding variants of the below included for disassembly only
// Most significant word multiply // Most significant word multiply
def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, class T2SMMUL<bits<4> op7_4, string opc, list<dag> pattern>
"smmul", "\t$Rd, $Rn, $Rm", : T2ThreeReg<(outs rGPR:$Rd),
[(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>, (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
Requires<[IsThumb2, HasDSP]> { opc, "\t$Rd, $Rn, $Rm", pattern>,
let Inst{31-27} = 0b11111; Requires<[IsThumb2, HasDSP]> {
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b101;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
}
def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
"smmulr", "\t$Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b101; let Inst{22-20} = 0b101;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) let Inst{7-4} = op7_4;
} }
def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
rGPR:$Rm))]>;
def t2SMMULR : T2SMMUL<0b0001, "smmulr", []>;
def t2SMMLA : T2FourReg< class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc,
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, list<dag> pattern>
"smmla", "\t$Rd, $Rn, $Rm, $Ra", : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
[(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>, opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
Requires<[IsThumb2, HasDSP, UseMulOps]> { Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b101; let Inst{22-20} = op22_20;
let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) let Inst{7-4} = op7_4;
}
def t2SMMLAR: T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
"smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b101;
let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
}
def t2SMMLS: T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
"smmls", "\t$Rd, $Rn, $Rm, $Ra",
[(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b110;
let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
}
def t2SMMLSR:T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
"smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b110;
let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
} }
multiclass T2I_smul<string opc, SDNode opnode> { def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
!strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", []>;
[(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16), def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls",
(sext_inreg rGPR:$Rm, i16)))]>, [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>;
Requires<[IsThumb2, HasDSP]> { def t2SMMLSR:T2FourRegSMMLA<0b110, 0b0001, "smmlsr", []>;
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b00;
}
def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
!strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
(sra rGPR:$Rm, (i32 16))))]>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b01;
}
def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
!strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
(sext_inreg rGPR:$Rm, i16)))]>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b10;
}
def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
!strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
(sra rGPR:$Rm, (i32 16))))]>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b11;
}
def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc,
!strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", list<dag> pattern>
[]>, : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc,
Requires<[IsThumb2, HasDSP]> { "\t$Rd, $Rn, $Rm", pattern>,
let Inst{31-27} = 0b11111; Requires<[IsThumb2, HasDSP]> {
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b00;
}
def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
!strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
[]>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011; let Inst{22-20} = op22_20;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00; let Inst{7-6} = 0b00;
let Inst{5-4} = 0b01; let Inst{5-4} = op5_4;
} }
}
def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb",
[(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16),
multiclass T2I_smla<string opc, SDNode opnode> { (sext_inreg rGPR:$Rm, i16)))]>;
def BB : T2FourReg< def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt",
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16),
!strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", (sra rGPR:$Rm, (i32 16))))]>;
[(set rGPR:$Rd, (add rGPR:$Ra, def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb",
(opnode (sext_inreg rGPR:$Rn, i16), [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
(sext_inreg rGPR:$Rm, i16))))]>, (sext_inreg rGPR:$Rm, i16)))]>;
Requires<[IsThumb2, HasDSP, UseMulOps]> { def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt",
[(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
(sra rGPR:$Rm, (i32 16))))]>;
def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb", []>;
def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt", []>;
class T2FourRegSMLA<bits<2> op5_4, string opc, list<dag> pattern>
: T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16,
opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001; let Inst{22-20} = 0b001;
let Inst{7-6} = 0b00; let Inst{7-6} = 0b00;
let Inst{5-4} = 0b00; let Inst{5-4} = op5_4;
} }
def BT : T2FourReg< def t2SMLABB : T2FourRegSMLA<0b00, "smlabb",
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, [(set rGPR:$Rd, (add rGPR:$Ra,
!strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", (mul (sext_inreg rGPR:$Rn, i16),
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16), (sext_inreg rGPR:$Rm, i16))))]>;
(sra rGPR:$Rm, (i32 16)))))]>, def t2SMLABT : T2FourRegSMLA<0b01, "smlabt",
Requires<[IsThumb2, HasDSP, UseMulOps]> { [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sext_inreg rGPR:$Rn, i16),
let Inst{31-27} = 0b11111; (sra rGPR:$Rm, (i32 16)))))]>;
let Inst{26-23} = 0b0110; def t2SMLATB : T2FourRegSMLA<0b10, "smlatb",
let Inst{22-20} = 0b001; [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
let Inst{7-6} = 0b00; (sext_inreg rGPR:$Rm, i16))))]>;
let Inst{5-4} = 0b01; def t2SMLATT : T2FourRegSMLA<0b11, "smlatt",
} [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
(sra rGPR:$Rm, (i32 16)))))]>;
def TB : T2FourReg< def t2SMLAWB : T2FourRegSMLA<0b00, "smlawb", []> {
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, let Inst{22-20} = 0b011;
!strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", }
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)), def t2SMLAWT : T2FourRegSMLA<0b01, "smlawt", []> {
(sext_inreg rGPR:$Rm, i16))))]>, let Inst{22-20} = 0b011;
Requires<[IsThumb2, HasDSP, UseMulOps]> { }
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; class T2SMLAL<bits<3> op22_20, bits<4> op7_4, string opc, list<dag> pattern>
let Inst{22-20} = 0b001; : T2FourReg_mac<1, op22_20, op7_4,
let Inst{7-6} = 0b00; (outs rGPR:$Ra, rGPR:$Rd),
let Inst{5-4} = 0b10; (ins rGPR:$Rn, rGPR:$Rm),
} IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]>;
def TT : T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
!strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
(sra rGPR:$Rm, (i32 16)))))]>,
Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b11;
}
def WB : T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
!strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
[]>,
Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011;
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b00;
}
def WT : T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
!strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
[]>,
Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011;
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b01;
}
}
defm t2SMUL : T2I_smul<"smul", mul>;
defm t2SMLA : T2I_smla<"smla", mul>;
// Halfword multiple accumulate long: SMLAL<x><y> // Halfword multiple accumulate long: SMLAL<x><y>
def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd), def t2SMLALBB : T2SMLAL<0b100, 0b1000, "smlalbb", []>;
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm", def t2SMLALBT : T2SMLAL<0b100, 0b1001, "smlalbt", []>;
[/* For disassembly only; pattern left blank */]>, def t2SMLALTB : T2SMLAL<0b100, 0b1010, "smlaltb", []>;
Requires<[IsThumb2, HasDSP]>; def t2SMLALTT : T2SMLAL<0b100, 0b1011, "smlaltt", []>;
def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm", class T2DualHalfMul<bits<3> op22_20, bits<4> op7_4, string opc>
[/* For disassembly only; pattern left blank */]>, : T2ThreeReg_mac<0, op22_20, op7_4,
Requires<[IsThumb2, HasDSP]>; (outs rGPR:$Rd),
def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm", IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm", []>,
[/* For disassembly only; pattern left blank */]>, Requires<[IsThumb2, HasDSP]> {
Requires<[IsThumb2, HasDSP]>;
def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsThumb2, HasDSP]>;
// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
def t2SMUAD: T2ThreeReg_mac<
0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]> {
let Inst{15-12} = 0b1111; let Inst{15-12} = 0b1111;
} }
def t2SMUADX:T2ThreeReg_mac<
0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>, def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad">;
Requires<[IsThumb2, HasDSP]> { def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx">;
let Inst{15-12} = 0b1111; def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd">;
} def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx">;
def t2SMUSD: T2ThreeReg_mac<
0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), class T2DualHalfMulAdd<bits<3> op22_20, bits<4> op7_4, string opc>
IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>, : T2FourReg_mac<0, op22_20, op7_4,
Requires<[IsThumb2, HasDSP]> { (outs rGPR:$Rd),
let Inst{15-12} = 0b1111; (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra),
} IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra", []>,
def t2SMUSDX:T2ThreeReg_mac< Requires<[IsThumb2, HasDSP]>;
0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>, def t2SMLAD : T2DualHalfMulAdd<0b010, 0b0000, "smlad">;
Requires<[IsThumb2, HasDSP]> { def t2SMLADX : T2DualHalfMulAdd<0b010, 0b0001, "smladx">;
let Inst{15-12} = 0b1111; def t2SMLSD : T2DualHalfMulAdd<0b100, 0b0000, "smlsd">;
} def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx">;
def t2SMLAD : T2FourReg_mac<
0, 0b010, 0b0000, (outs rGPR:$Rd), class T2DualHalfMulAddLong<bits<3> op22_20, bits<4> op7_4, string opc>
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad", : T2FourReg_mac<1, op22_20, op7_4,
"\t$Rd, $Rn, $Rm, $Ra", []>, (outs rGPR:$Ra, rGPR:$Rd),
Requires<[IsThumb2, HasDSP]>; (ins rGPR:$Rn, rGPR:$Rm),
def t2SMLADX : T2FourReg_mac< IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
0, 0b010, 0b0001, (outs rGPR:$Rd), Requires<[IsThumb2, HasDSP]>;
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
"\t$Rd, $Rn, $Rm, $Ra", []>, def t2SMLALD : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">;
Requires<[IsThumb2, HasDSP]>; def t2SMLALDX : T2DualHalfMulAddLong<0b100, 0b1101, "smlaldx">;
def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd), def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">;
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd", def t2SMLSLDX : T2DualHalfMulAddLong<0b101, 0b1101, "smlsldx">;
"\t$Rd, $Rn, $Rm, $Ra", []>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
"\t$Rd, $Rn, $Rm, $Ra", []>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
"\t$Ra, $Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
"\t$Ra, $Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
"\t$Ra, $Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
"\t$Ra, $Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Division Instructions. // Division Instructions.
// Signed and unsigned division on v7-M // Signed and unsigned division on v7-M
// //
def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV, def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
"sdiv", "\t$Rd, $Rn, $Rm", "sdiv", "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>, [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines

test/CodeGen/ARM/longMAC.ll

; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-LE
; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s --check-prefix=CHECK-V7-LE ; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s --check-prefix=CHECK-V7-LE
; RUN: llc -mtriple=armeb-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE ; RUN: llc -mtriple=armeb-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
; RUN: llc -mtriple=armebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7-BE ; RUN: llc -mtriple=armebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7-BE
; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7-THUMB
; RUN: llc -mtriple=thumbebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7-THUMB-BE
; Check generated signed and unsigned multiply accumulate long. ; Check generated signed and unsigned multiply accumulate long.
define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) { define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
;CHECK-LABEL: MACLongTest1: ;CHECK-LABEL: MACLongTest1:
;CHECK: umlal ;CHECK: umlal
%conv = zext i32 %a to i64 %conv = zext i32 %a to i64
%conv1 = zext i32 %b to i64 %conv1 = zext i32 %b to i64
%mul = mul i64 %conv1, %conv %mul = mul i64 %conv1, %conv
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines;CHECK-NOT: smlal
%shl = shl i64 %mul, 32 %shl = shl i64 %mul, 32
%or = or i64 %and, %shl %or = or i64 %and, %shl
%add = add i64 %or, %acc %add = add i64 %or, %acc
ret i64 %add ret i64 %add
} }
define i64 @MACLongTest9(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) { define i64 @MACLongTest9(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) {
;CHECK-LABEL: MACLongTest9: ;CHECK-LABEL: MACLongTest9:
;CHECK-V7-LE:umaal ;CHECK-V7-LE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-BE:umaal ;CHECK-V7-LE: mov r0, [[RDLO]]
;CHECK-V7-LE: mov r1, [[RDHI]]
;CHECK-V7-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-BE: mov r0, [[RDHI]]
;CHECK-V7-BE: mov r1, [[RDLO]]
;CHECK-V7-THUMB: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-THUMB: mov r0, [[RDLO]]
;CHECK-V7-THUMB: mov r1, [[RDHI]]
;CHECK-V7-THUMB-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
;CHECK-NOT:umaal ;CHECK-NOT:umaal
%conv = zext i32 %lhs to i64 %conv = zext i32 %lhs to i64
%conv1 = zext i32 %rhs to i64 %conv1 = zext i32 %rhs to i64
%mul = mul nuw i64 %conv1, %conv %mul = mul nuw i64 %conv1, %conv
%conv2 = zext i32 %lo to i64 %conv2 = zext i32 %lo to i64
%add = add i64 %mul, %conv2 %add = add i64 %mul, %conv2
%conv3 = zext i32 %hi to i64 %conv3 = zext i32 %hi to i64
%add2 = add i64 %add, %conv3 %add2 = add i64 %add, %conv3
ret i64 %add2 ret i64 %add2
} }
define i64 @MACLongTest10(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) { define i64 @MACLongTest10(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) {
;CHECK-LABEL: MACLongTest10: ;CHECK-LABEL: MACLongTest10:
;CHECK-V7-LE:umaal ;CHECK-V7-LE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-BE:umaal ;CHECK-V7-LE: mov r0, [[RDLO]]
;CHECK-V7-LE: mov r1, [[RDHI]]
;CHECK-V7-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-BE: mov r0, [[RDHI]]
;CHECK-V7-BE: mov r1, [[RDLO]]
;CHECK-V7-THUMB: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-THUMB: mov r0, [[RDLO]]
;CHECK-V7-THUMB: mov r1, [[RDHI]]
;CHECK-V7-THUMB-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
;CHECK-NOT:umaal ;CHECK-NOT:umaal
%conv = zext i32 %lhs to i64 %conv = zext i32 %lhs to i64
%conv1 = zext i32 %rhs to i64 %conv1 = zext i32 %rhs to i64
%mul = mul nuw i64 %conv1, %conv %mul = mul nuw i64 %conv1, %conv
%conv2 = zext i32 %lo to i64 %conv2 = zext i32 %lo to i64
%conv3 = zext i32 %hi to i64 %conv3 = zext i32 %hi to i64
%add = add i64 %conv2, %conv3 %add = add i64 %conv2, %conv3
%add2 = add i64 %add, %mul %add2 = add i64 %add, %mul
ret i64 %add2 ret i64 %add2
} }