[mips] Update the P5600 scheduler for isComplete = 1

[sdardis]

Summary

These changes update the schedule model for the P5600 and include the
rest of the MSA and MIPS32R5 instruction set.

[sdardis]

Remove repeated resource use for co-processor 0 instructions.

[sdardis]

Wrong diff uploaded.

[sdardis]

Ping.

[dsanders]

LGTM

lib/Target/Mips/MipsScheduleP5600.td

def : ItinRW<[P5600WriteJump], [II_B, II_BCC, II_BCCZ, II_BCCZAL, II_J, II_JR,
                                 II_SYSCALL, II_BREAK, II_SDBBP, II_SSNOP,
                                 II_TEQ, II_TEQI, II_TGE, II_TGEI, II_TGEIU,
                                 II_TGEU, II_TLT, II_TLTI, II_TLTU, II_TNE,
                                 II_TNEI, II_TRAP, II_TTLTIU, II_WAIT,
                                 II_PAUSE]>;
 
 def : ItinRW<[P5600WriteJumpAndLink], [II_JAL, II_JALR, II_JALR_HB]>;
 
-def P5600COP0 : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]>;
+def P5600COP0 : SchedWriteRes<[P5600IssueCTISTD]>;
 
 def : ItinRW<[P5600COP0], [II_TLBINV, II_TLBINVF, II_TLBP, II_TLBR, II_TLBWI,
                            II_TLBWR, II_MFC0, II_MTC0]>;
 // LDST Pipeline
 // -------------
 
 def P5600WriteLoad : SchedWriteRes<[P5600IssueLDST]> {
   let Latency = 4;