[SystemZ] Add support for the .insn directive

[• zhanjunl]

Summary

Add support for the .insn directive.

.insn is an s390 specific directive that allows encoding of an instruction
instead of using a mnemonic. The motivating case is some code in node.js that
requires support for the .insn directive.

[• koriakin]

lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

825

.short, .long. .quad are already supported by common code.

[• koriakin]

lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

825

Also, .word would be better implemented by using addAliasForDirective instead of reimplementing the handler.

[• koriakin]

lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

517

should be NumOperands

521

For better or worse, gas considers the immediate here to be pc-relative and shifted.

523

Also pc-relative and shifted.

541

Likewise pc-relative and shifted.

562

This is wrong.

564

Likewise.

566

Likewise.

669

Looks like a job for llvm_unreachable.

881

Would be nice to have "too few operands" error here.

891

gas also accepts plain numbers whenever registers are accepted - while normally it's not much of an issue, it needs to be supported here, as the 'R' fields in many formats are also used for immediate arguments (eg. CC mask) for some instructions.

915

Needs verification of immediate range (or at least clipping off the extra bits).

[• koriakin]

See inline comments. Also, this might not be the good level to have .insn handling - for one, we forfeit any hope of handling fixups in immediate operands (which is necessary to handle pc-relative forms correctly). It might be better to represent these directives as special machine instructions, one per form.

[• koriakin]

Oh, and the .word change should be split off (it'll likely be a one-liner using the alias functionality)

[• koriakin]

test/MC/SystemZ/directive-insn.s

11

Please cross-check this test with gas, this line (and some others) assembles differently...

[uweigand]

test/MC/SystemZ/directive-insn.s

5

We really should have tests for all the formats, since they encode differently.

I do in fact see instructions already recognized for several of these:
RIE: CRJ*, RxSBG, ...
RRF: CRT*, LOCR(G), PPA, many FP insns
SS: MVC, NC, OC, XC, CLC
RSE: SRLG etc, LMG/STMG, ...

For the others, it might be good to add some instructions in those formats, they can be useful for inline asm anyway.

[• zhanjunl]

From my understanding, gas only supports some of the possible s390 instruction formats when using ".insn". For example, the "ri" format in the insn directive corresponds to the RI-a format, which uses an immediate field and not a relative-immediate field. Therefore, for the .insn directive specifically:

ri = RI-a
rie = RIE-d
ril = RIL-a

I tried assembling a sample .insn directive with gas:

        .text
        .globl  main
        .type   main,@function
main:
        lghi    %r2, 0
#       brct %r2,.label
        .insn ri,0xa7060000,%r2,.label
.label:
        br      %r14
.Lfunc_end0:
        .size   main, .Lfunc_end0-main

gas will assemble the above code with no errors, but when I do an objdump of the object file, I see:

temp.o:     file format elf64-s390


Disassembly of section .text:

0000000000000000 <main>:
   0:   a7 29 00 00             lghi    %r2,0
   4:   a7 26 00 00             brct    %r2,4 <main+0x4>

0000000000000008 <.label>:
   8:   07 fe                   br      %r14
   a:   07 07                   nopr    %r7

So it looks like it was able to get the correct instruction mnemonic, but it silently fails when trying to encode the label into the instruction. This was my understanding when supporting the .insn, and so I didn't expect to have to do any fixups. Unless I'm mistaken?

[• zhanjunl]

Once I figure out if we're sticking with this implementation, I'll continue working on this and fix up all the comments that have been made. Thanks for the quick and thorough review guys!

test/MC/SystemZ/directive-insn.s

5

Similar to the comment I added, rie corresponds with RIE-d instructions, of which I couldn't find any that clang supported.

Same with rrf (RRF-a,b), ss (SS-d), rse (I couldn't find an actual format that matched this class, as those instructions are RSY?).

[• koriakin]

In D21809#470546, @zhanjunl wrote:

From my understanding, gas only supports some of the possible s390 instruction formats when using ".insn". For example, the "ri" format in the insn directive corresponds to the RI-a format, which uses an immediate field and not a relative-immediate field. Therefore, for the .insn directive specifically:

ri = RI-a
rie = RIE-d
ril = RIL-a

I was refering to RIE, RIL, RSI with my comments about pc-relative operands, not RI. Here goes (gas):

nopr %r7      
.insn rie, 0xec0000000044, 1, 2, label
nopr %r7
label:

Disassembly of section .text:

0000000000000000 <label-0xa>:
   0:   07 07                   nopr    %r7
   2:   ec 12 00 04 00 44       brxhg   %r1,%r2,a <label>
   8:   07 07                   nopr    %r7

000000000000000a <label>:
   a:   07 07                   nopr    %r7

So this is definitely supported.

I tried assembling a sample .insn directive with gas:

        .text
        .globl  main
        .type   main,@function
main:
        lghi    %r2, 0
#       brct %r2,.label
        .insn ri,0xa7060000,%r2,.label
.label:
        br      %r14
.Lfunc_end0:
        .size   main, .Lfunc_end0-main

gas will assemble the above code with no errors, but when I do an objdump of the object file, I see:

temp.o:     file format elf64-s390


Disassembly of section .text:

0000000000000000 <main>:
   0:   a7 29 00 00             lghi    %r2,0
   4:   a7 26 00 00             brct    %r2,4 <main+0x4>

0000000000000008 <.label>:
   8:   07 fe                   br      %r14
   a:   07 07                   nopr    %r7

So it looks like it was able to get the correct instruction mnemonic, but it silently fails when trying to encode the label into the instruction. This was my understanding when supporting the .insn, and so I didn't expect to have to do any fixups. Unless I'm mistaken?

Again, this is RI, which gas considers to be RI-a, which is not PC-relative. Also, please disassemble your code with objdump -dr:

Disassembly of section .text:

0000000000000000 <main>:
   0:   a7 29 00 00             lghi    %r2,0
   4:   a7 26 00 00             brct    %r2,4 <main+0x4>
                        6: R_390_16     .text+0x8

0000000000000008 <.label>:
   8:   07 fe                   br      %r14
   a:   07 07                   nopr    %r7

Here goes the fixup.

[uweigand]

From my understanding, gas only supports some of the possible s390 instruction formats when using ".insn". For example, the "ri" format in the insn directive corresponds to the RI-a format, which uses an immediate field and not a relative-immediate field. Therefore, for the .insn directive specifically:

ri = RI-a
rie = RIE-d
ril = RIL-a

Well, sort of ... it is true that each .insn format corresponds to one specific s390 subformat, but for the most part, you can also use .insn to encode other subformats, e.g. by passing a mask in a register field, or by setting a field to 0. Existing code using inline asm does that ...

However, there are a few subformats that indeed currently cannot be encoded, e.g. RI-b or RI-c, the RI variants with a PC-relative operand. So my earlier comment was indeed not quite correct.

Looking at those formats again:

RIE: .insn directly models RIE-e, which is only used by BRXLG/BRXHG, which LLVM does not current have (but probably should). However, we can also map the RIE-b format as long as M3 is hard-coded in the opcode (which is used by CRJ et al), or the RIE-c format as long as I2 is hard-coded (which is used by CIJ et al). We can use a test using one of those to ensure the operand encoding works correctly. [ I mentioned RxSBG, but those actually cannot be encoded since the .insn rie format always has a PC-relative operand. ]

RRF: all variants (RRF-a ... RRF-e) can be modeled (as long as can we pass a mask in a register field), so really any of the RRF instructions can be used here. Most of those only use three fields, so in order to test all four we should use one of floating-point insns like LEDBRA.

RSE: in z/Architecture those are all now RSY, really ... so to test that .insn rse works, we can use any of the RSY instructions but simply only provide a short displacement

SS: this is indeed a bit difficult ... there are many SS subformats, and the instructions we currently support in LLVM (MVC etc) use the 8-bit length field, which cannot easily be represented with the .insn ss format

[• zhanjunl]

Reworked this diff to use MC instructions to parse and emit the directive. This allows handling of PC-relative operands for some of these directives. Also added some new instructions so that we can test the .insn directive for all formats.

[uweigand]

Thanks for the rework, this is looking much better now!

A couple of additional comments / requests:

Could you please split off adding those other insns like PR, MVCK, ... into a separate patch? This is really an independent change that can be reviewed separately and committed ahead of the .insn patch.

I don't really like the code duplication between the Insn / AsmInsn patterns. I can see why we need a isCodeGenOnly as well as a isAsmParserOnly pattern (so that the disassembler doesn't get confused), but those should then get generated from a multiclass template. See e.g. how this is done with the CompareBranches multiclass.

In addition, it doesn't seem a good idea to have the AsmInsn patterns recognize "instructions" like InsnE. This means that assembly files that contain the literal string InsnE will get recognized here, which is not really what we want. I'm wondering if we cannot simply also use ".insn e,..." as the string for the AsmInsn patterns as well -- if we do that, I think the auto-generated matchers should use literal string matching to detect the correct pattern to use, which means that the extra table getOpcodeFromFormat would no longer be necessary -- another duplication eliminated.

Your routine parseAnyGRFPRegister accepts integers, %rX and %fX. GAS in addition accepts %vX (for X < 16) as well.

For consistency, I think DirectiveInsnRSE should derive from (a newly created) InsnRSE, just like all the other DirectiveInsn patterns.

[uweigand]

In D21809#502103, @uweigand wrote:

I don't really like the code duplication between the Insn / AsmInsn patterns. I can see why we need a isCodeGenOnly as well as a isAsmParserOnly pattern (so that the disassembler doesn't get confused), but those should then get generated from a multiclass template. See e.g. how this is done with the CompareBranches multiclass.

In addition, it doesn't seem a good idea to have the AsmInsn patterns recognize "instructions" like InsnE. This means that assembly files that contain the literal string InsnE will get recognized here, which is not really what we want. I'm wondering if we cannot simply also use ".insn e,..." as the string for the AsmInsn patterns as well -- if we do that, I think the auto-generated matchers should use literal string matching to detect the correct pattern to use, which means that the extra table getOpcodeFromFormat would no longer be necessary -- another duplication eliminated.

Following up on myself here, actually I don't think we even need the isCodeGenOnly variants at all. Simply having the isAsmParserOnly variants should suffice (we only need it for the asm parser after all ...).

[• zhanjunl]

In D21809#502103, @uweigand wrote:

Could you please split off adding those other insns like PR, MVCK, ... into a separate patch? This is really an independent change that can be reviewed separately and committed ahead of the .insn patch.

I'll split off the changes into a different diff.

I don't really like the code duplication between the Insn / AsmInsn patterns. I can see why we need a isCodeGenOnly as well as a isAsmParserOnly pattern (so that the disassembler doesn't get confused), but those should then get generated from a multiclass template. See e.g. how this is done with the CompareBranches multiclass.

In addition, it doesn't seem a good idea to have the AsmInsn patterns recognize "instructions" like InsnE. This means that assembly files that contain the literal string InsnE will get recognized here, which is not really what we want. I'm wondering if we cannot simply also use ".insn e,..." as the string for the AsmInsn patterns as well -- if we do that, I think the auto-generated matchers should use literal string matching to detect the correct pattern to use, which means that the extra table getOpcodeFromFormat would no longer be necessary -- another duplication eliminated.

I would have liked to use ".insn e" for the mnemonic as well, but from my understanding, TableGen removes all white spaces after parsing the string for tokens, so I couldn't find a way to get TableGen to generate ".insn e" as the asm mnemonic. Which is why I created two duplicated instructions. I'll try to do a bit more digging to see if there's another way around it.

Your routine parseAnyGRFPRegister accepts integers, %rX and %fX. GAS in addition accepts %vX (for X < 16) as well.

I wasn't sure whether vector registers should be recognized since there are no .insn directives for vector instructions, but I guess for GCC compatibility it makes sense. I'll fix this up.

For consistency, I think DirectiveInsnRSE should derive from (a newly created) InsnRSE, just like all the other DirectiveInsn patterns.

I'm not sure we want to have a newly created InsnRSE, since RSE isn't a valid instruction format and I don't want to confuse any future users into thinking it's a valid format to use.

[uweigand]

In D21809#504834, @zhanjunl wrote:

In D21809#502103, @uweigand wrote:

In addition, it doesn't seem a good idea to have the AsmInsn patterns recognize "instructions" like InsnE. This means that assembly files that contain the literal string InsnE will get recognized here, which is not really what we want. I'm wondering if we cannot simply also use ".insn e,..." as the string for the AsmInsn patterns as well -- if we do that, I think the auto-generated matchers should use literal string matching to detect the correct pattern to use, which means that the extra table getOpcodeFromFormat would no longer be necessary -- another duplication eliminated.

I would have liked to use ".insn e" for the mnemonic as well, but from my understanding, TableGen removes all white spaces after parsing the string for tokens, so I couldn't find a way to get TableGen to generate ".insn e" as the asm mnemonic. Which is why I created two duplicated instructions. I'll try to do a bit more digging to see if there's another way around it.

Well, the mnemonic would be just ".insn", and "e" would be the first operand, decoded as fixed string. If you simply use ".insn e, ..." as an AsmParser pattern, you should see something like this in the generated SystemZGenAsmMatcher.inc file:

static const MatchEntry MatchTable0[] = {

{ 0 /* .insn */, SystemZ::AsmInsnE, Convert__U16Imm1_1, 0, { MCK_e, MCK_U16Imm }, },
{ 0 /* .insn */, SystemZ::AsmInsnRI, Convert__U32Imm1_1__AnyGRFP1_2__S16Imm1_3, 0, { MCK_ri, MCK_U32Imm, MCK_AnyGRFP, MCK_S16Imm }, },
{ 0 /* .insn */, SystemZ::AsmInsnRIE, Convert__U48Imm1_1__AnyGRFP1_2__AnyGRFP1_3__PCRel161_4, 0, { MCK_rie, MCK_U48Imm, MCK_AnyGRFP, MCK_AnyGRFP, MCK_PCRel16 }, },

where the MCK_e, MCK_ri etc are matched as string constants via matchTokenString.

For consistency, I think DirectiveInsnRSE should derive from (a newly created) InsnRSE, just like all the other DirectiveInsn patterns.

I'm not sure we want to have a newly created InsnRSE, since RSE isn't a valid instruction format and I don't want to confuse any future users into thinking it's a valid format to use.

Hmm. Maybe just use DirectiveInsnRSY then, since RSE is just the same as RSY except that only 12-bit displacements are used (which the insn pattern already enforces via addr12only).

[• zhanjunl]

In D21809#504840, @uweigand wrote:

Well, the mnemonic would be just ".insn", and "e" would be the first operand, decoded as fixed string. If you simply use ".insn e, ..." as an AsmParser pattern, you should see something like this in the generated SystemZGenAsmMatcher.inc file:

static const MatchEntry MatchTable0[] = {

{ 0 /* .insn */, SystemZ::AsmInsnE, Convert__U16Imm1_1, 0, { MCK_e, MCK_U16Imm }, },
{ 0 /* .insn */, SystemZ::AsmInsnRI, Convert__U32Imm1_1__AnyGRFP1_2__S16Imm1_3, 0, { MCK_ri, MCK_U32Imm, MCK_AnyGRFP, MCK_S16Imm }, },
{ 0 /* .insn */, SystemZ::AsmInsnRIE, Convert__U48Imm1_1__AnyGRFP1_2__AnyGRFP1_3__PCRel161_4, 0, { MCK_rie, MCK_U48Imm, MCK_AnyGRFP, MCK_AnyGRFP, MCK_PCRel16 }, },

where the MCK_e, MCK_ri etc are matched as string constants via matchTokenString.

Hmm, that table is used for matching the instruction after the instruction has been parsed. ParseInstruction uses the OperandMatchTable for parsing operands, which looks like this if I use the ".insn e,..." forms.

static const OperandMatchEntry OperandMatchTable[2076] = {
  { 0, 0 /* .insn */, MCK_BDAddr64Disp12, 4 /* 2 */ },
  { 0, 0 /* .insn */, MCK_AnyGRFP, 4 /* 2 */ },
  { 0, 0 /* .insn */, MCK_PCRel32, 8 /* 3 */ },
  { 0, 0 /* .insn */, MCK_AnyGRFP, 12 /* 2, 3 */ },

The code for parsing operands goes through that table and for every entry that matches the mnemonic, will try to parse the current operand based on the current entry. So for example,

.insn ri,0xa7080000,%r1,1

Based on the table, operand 3 ("1") could be a PCRel32 or a register, or an immediate. The parser will try to parse operand 3 as a PC-rel first because it's the first entry, which means that "1" could be parsed as a pc-rel operand, when it should have been an immediate. The same goes for immediate vs register, immediate vs address, etc. I'm not sure how to pick the right operand parser routine, and I'm not sure it's even possible using ParseInstruction based on the way the table is set up.

Unless there's something I'm missing, the only solution I could come up with is to write a custom parser that parses everything for the .insn directive, and use MatchTable0 to make sure that the operands are correct, but there would be some overlap in code with the other custom parser routines.

[uweigand]

In D21809#505251, @zhanjunl wrote:

Hmm, that table is used for matching the instruction after the instruction has been parsed. ParseInstruction uses the OperandMatchTable for parsing operands, which looks like this if I use the ".insn e,..." forms.

Ah, I completely forgot about this two-step process. Yes, this is quite annyoing and would not work as I thought.

Unless there's something I'm missing, the only solution I could come up with is to write a custom parser that parses everything for the .insn directive, and use MatchTable0 to make sure that the operands are correct, but there would be some overlap in code with the other custom parser routines.

I don't see any really clever option here either. Probably the best way forward would be to go back to a custom operand parsing, based on a table similar to your original approach, where for each format you have a list of operand parser routines you call in sequence to collect all the operands. These routines should be the same that would also be called from the auto-generated operand parser, so e.g. for InsnRIL you'd call parseAnyGRFP and then parsePCRel32.

For code generation you'd then use the Insn* patterns (marked isCodeGenOnly) of your current approach.

This is still a bit annoying since the operand info is now still duplicated between the patterns and your special table. But I guess that's the best we can for now without major reworks to TableGen.

[• zhanjunl]

Created a custom table with operand information to parse the different formats, which calls the same parse* routines that are used by TableGen generated code.
Removed the AsmInsn* variants and allow vector registers to be recognized when parsing registers for the insn directive.

[uweigand]

Thanks for working through all those changes. This version looks good to me.

[rogfer01]

llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

512–520 ↗

(On Diff #67173)

This fails to build in Windows with Visual Studio 2013 with debugging enabled because of some debugging macro disaster in the std::equal_range used below.

Do you mind if I add this extra operator() like below?

  bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
	  return LHS.Format < RHS.Format;
  }

I know it looks silly but this fails to build from source otherwise when debugging is enabled.

Thank you

[• zhanjunl]

llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

512–520 ↗

(On Diff #67173)

Sure, I don't see anything wrong with that. Sorry for the build break.

lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/SystemZMCTargetDesc.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
public:
   bool isADDR128() const { return false; }
   bool isFP32() const { return isReg(FP32Reg); }
   bool isFP64() const { return isReg(FP64Reg); }
   bool isFP128() const { return isReg(FP128Reg); }
   bool isVR32() const { return isReg(VR32Reg); }
   bool isVR64() const { return isReg(VR64Reg); }
   bool isVF128() const { return false; }
   bool isVR128() const { return isReg(VR128Reg); }
+  bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
   bool isU1Imm() const { return isImm(0, 1); }
   bool isU2Imm() const { return isImm(0, 3); }
   bool isU3Imm() const { return isImm(0, 7); }
   bool isU4Imm() const { return isImm(0, 15); }
   bool isU6Imm() const { return isImm(0, 63); }
   bool isU8Imm() const { return isImm(0, 255); }
   bool isS8Imm() const { return isImm(-128, 127); }
   bool isU12Imm() const { return isImm(0, 4095); }
   bool isU16Imm() const { return isImm(0, 65535); }
   bool isS16Imm() const { return isImm(-32768, 32767); }
   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
+  bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
 };
 
 class SystemZAsmParser : public MCTargetAsmParser {
 #define GET_ASSEMBLER_HEADER
 #include "SystemZGenAsmMatcher.inc"
 
 private:
   MCAsmParser &Parser;
private:
 
   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
                      bool IsAddress = false);
 
   OperandMatchResultTy parseRegister(OperandVector &Operands,
                                      RegisterGroup Group, const unsigned *Regs,
                                      RegisterKind Kind);
 
+  OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
+
   bool parseAddress(unsigned &Base, const MCExpr *&Disp,
                     unsigned &Index, bool &IsVector, const MCExpr *&Length,
                     const unsigned *Regs, RegisterKind RegKind);
 
+  bool ParseDirectiveInsn(SMLoc L);
+
   OperandMatchResultTy parseAddress(OperandVector &Operands,
                                     MemoryKind MemKind, const unsigned *Regs,
                                     RegisterKind RegKind);
 
   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
                                   int64_t MaxVal, bool AllowTLS);
 
   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
OperandMatchResultTy parseVR64(OperandVector &Operands) {
     return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
   }
   OperandMatchResultTy parseVF128(OperandVector &Operands) {
     llvm_unreachable("Shouldn't be used as an operand");
   }
   OperandMatchResultTy parseVR128(OperandVector &Operands) {
     return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
   }
+  OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
+    return parseAnyRegister(Operands);
+  }
   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
     return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
   }
   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
     return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
   }
   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
     return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);

 };
 } // end anonymous namespace
 
 #define GET_REGISTER_MATCHER
 #define GET_SUBTARGET_FEATURE_NAME
 #define GET_MATCHER_IMPLEMENTATION
 #include "SystemZGenAsmMatcher.inc"
 
+// Used for the .insn directives; contains information needed to parse the
+// operands in the directive.
+struct InsnMatchEntry {
+  StringRef Format;
+  uint64_t Opcode;
+  int32_t NumOperands;
+  MatchClassKind OperandKinds[5];
+};
+
+// For equal_range comparison.
+struct CompareInsn {
+  bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
+    return LHS.Format < RHS;
+  }
+  bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
+    return LHS < RHS.Format;
+  }
+};
+
+// Table initializing information for parsing the .insn directive.
+static struct InsnMatchEntry InsnMatchTable[] = {
+  /* Format, Opcode, NumOperands, OperandKinds */
+  { "e", SystemZ::InsnE, 1,
+    { MCK_U16Imm } },
+  { "ri", SystemZ::InsnRI, 3,
+    { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
+  { "rie", SystemZ::InsnRIE, 4,
+    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
+  { "ril", SystemZ::InsnRIL, 3,
+    { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
+  { "rilu", SystemZ::InsnRILU, 3,
+    { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
+  { "ris", SystemZ::InsnRIS, 5,
+    { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
+  { "rr", SystemZ::InsnRR, 3,
+    { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
+  { "rre", SystemZ::InsnRRE, 3,
+    { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
+  { "rrf", SystemZ::InsnRRF, 5,
+    { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
+  { "rrs", SystemZ::InsnRRS, 5,
+    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
+  { "rs", SystemZ::InsnRS, 4,
+    { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
+  { "rse", SystemZ::InsnRSE, 4,
+    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
+  { "rsi", SystemZ::InsnRSI, 4,
+    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
+  { "rsy", SystemZ::InsnRSY, 4,
+    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
+  { "rx", SystemZ::InsnRX, 3,
+    { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
+  { "rxe", SystemZ::InsnRXE, 3,
+    { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
+  { "rxf", SystemZ::InsnRXF, 4,
+    { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
+  { "rxy", SystemZ::InsnRXY, 3,
+    { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
+  { "s", SystemZ::InsnS, 2,
+    { MCK_U32Imm, MCK_BDAddr64Disp12 } },
+  { "si", SystemZ::InsnSI, 3,
+    { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
+  { "sil", SystemZ::InsnSIL, 3,
+    { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
+  { "siy", SystemZ::InsnSIY, 3,
+    { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
+  { "ss", SystemZ::InsnSS, 4,
+    { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
+  { "sse", SystemZ::InsnSSE, 3,
+    { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
+  { "ssf", SystemZ::InsnSSF, 4,
+    { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
+};
+
 void SystemZOperand::print(raw_ostream &OS) const {
   llvm_unreachable("Not implemented");
 }
 
 // Parse one register of the form %<prefix><number>.
 bool SystemZAsmParser::parseRegister(Register &Reg) {
   Reg.StartLoc = Parser.getTok().getLoc();
 
SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
   if (parseRegister(Reg, Group, Regs, IsAddress))
     return MatchOperand_ParseFail;
 
   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
                                                Reg.StartLoc, Reg.EndLoc));
   return MatchOperand_Success;
 }
 
+// Parse any type of register (including integers) and add it to Operands.
+SystemZAsmParser::OperandMatchResultTy
+SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
+  // Handle integer values.
+  if (Parser.getTok().is(AsmToken::Integer)) {
+    const MCExpr *Register;
+    SMLoc StartLoc = Parser.getTok().getLoc();
+    if (Parser.parseExpression(Register))
+      return MatchOperand_ParseFail;
+
+    if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
+      int64_t Value = CE->getValue();
+      if (Value < 0 || Value > 15) {
+        Error(StartLoc, "invalid register");
+        return MatchOperand_ParseFail;
+      }
+    }
+
+    SMLoc EndLoc =
+      SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
+
+    Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
+  }
+  else {
+    Register Reg;
+    if (parseRegister(Reg))
+      return MatchOperand_ParseFail;
+
+    // Map to the correct register kind.
+    RegisterKind Kind;
+    unsigned RegNo;
+    if (Reg.Group == RegGR) {
+      Kind = GR64Reg;
+      RegNo = SystemZMC::GR64Regs[Reg.Num];
+    }
+    else if (Reg.Group == RegFP) {
+      Kind = FP64Reg;
+      RegNo = SystemZMC::FP64Regs[Reg.Num];
+    }
+    else if (Reg.Group == RegV) {
+      Kind = VR128Reg;
+      RegNo = SystemZMC::VR128Regs[Reg.Num];
+    }
+    else {
+      return MatchOperand_ParseFail;
+    }
+
+    Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
+                                                 Reg.StartLoc, Reg.EndLoc));
+  }
+  return MatchOperand_Success;
+}
+
 // Parse a memory operand into Base, Disp, Index and Length.
 // Regs maps asm register numbers to LLVM register numbers and RegKind
 // says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
                                     unsigned &Index, bool &IsVector,
                                     const MCExpr *&Length, const unsigned *Regs,
                                     RegisterKind RegKind) {
   // Parse the displacement, which must always be present.
SMLoc EndLoc =
     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
                                                Index, Length, StartLoc,
                                                EndLoc));
   return MatchOperand_Success;
 }
 
 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
+  StringRef IDVal = DirectiveID.getIdentifier();
+
+  if (IDVal == ".insn")
+    return ParseDirectiveInsn(DirectiveID.getLoc());
+
+  return true;
+}
+
+/// ParseDirectiveInsn
+/// ::= .insn [ format, encoding, (operands (, operands)*) ]
+bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
+  MCAsmParser &Parser = getParser();
+
+  // Expect instruction format as identifier.
+  StringRef Format;
+  SMLoc ErrorLoc = Parser.getTok().getLoc();
+  if (Parser.parseIdentifier(Format))
+    return Error(ErrorLoc, "expected instruction format");
+
+  SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
+
+  // Find entry for this format in InsnMatchTable.
+  auto EntryRange =
+    std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
+                     Format, CompareInsn());
+
+  // If first == second, couldn't find a match in the table.
+  if (EntryRange.first == EntryRange.second)
+    return Error(ErrorLoc, "unrecognized format");
+
+  struct InsnMatchEntry *Entry = EntryRange.first;
+
+  // Format should match from equal_range.
+  assert(Entry->Format == Format);
+
+  // Parse the following operands using the table's information.
+  for (int i = 0; i < Entry->NumOperands; i++) {
+    MatchClassKind Kind = Entry->OperandKinds[i];
+
+    SMLoc StartLoc = Parser.getTok().getLoc();
+
+    // Always expect commas as separators for operands.
+    if (getLexer().isNot(AsmToken::Comma))
+      return Error(StartLoc, "unexpected token in directive");
+    Lex();
+
+    // Parse operands.
+    OperandMatchResultTy ResTy;
+    if (Kind == MCK_AnyReg)
+      ResTy = parseAnyReg(Operands);
+    else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
+      ResTy = parseBDXAddr64(Operands);
+    else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
+      ResTy = parseBDAddr64(Operands);
+    else if (Kind == MCK_PCRel32)
+      ResTy = parsePCRel32(Operands);
+    else if (Kind == MCK_PCRel16)
+      ResTy = parsePCRel16(Operands);
+    else {
+      // Only remaining operand kind is an immediate.
+      const MCExpr *Expr;
+      SMLoc StartLoc = Parser.getTok().getLoc();
+
+      // Expect immediate expression.
+      if (Parser.parseExpression(Expr))
+        return Error(StartLoc, "unexpected token in directive");
+
+      SMLoc EndLoc =
+        SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
+
+      Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
+      ResTy = MatchOperand_Success;
+    }
+
+    if (ResTy != MatchOperand_Success)
       return true;
   }
 
+  // Build the instruction with the parsed operands.
+  MCInst Inst = MCInstBuilder(Entry->Opcode);
+
+  for (size_t i = 0; i < Operands.size(); i++) {
+    MCParsedAsmOperand &Operand = *Operands[i];
+    MatchClassKind Kind = Entry->OperandKinds[i];
+
+    // Verify operand.
+    unsigned Res = validateOperandClass(Operand, Kind);
+    if (Res != Match_Success)
+      return Error(Operand.getStartLoc(), "unexpected operand type");
+
+    // Add operands to instruction.
+    SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
+    if (ZOperand.isReg())
+      ZOperand.addRegOperands(Inst, 1);
+    else if (ZOperand.isMem(BDMem))
+      ZOperand.addBDAddrOperands(Inst, 2);
+    else if (ZOperand.isMem(BDXMem))
+      ZOperand.addBDXAddrOperands(Inst, 3);
+    else if (ZOperand.isImm())
+      ZOperand.addImmOperands(Inst, 1);
+    else
+      llvm_unreachable("unexpected operand type");
+  }
+
+  // Emit as a regular instruction.
+  Parser.getStreamer().EmitInstruction(Inst, getSTI());
+
+  return false;
+}
+
 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
                                      SMLoc &EndLoc) {
   Register Reg;
   if (parseRegister(Reg))
     return true;
   if (Reg.Group == RegGR)
     RegNo = SystemZMC::GR64Regs[Reg.Num];
   else if (Reg.Group == RegFP)

lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.h

private:
   void printU6ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printS8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printU8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printU12ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printS16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printU16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printS32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printU32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+  void printU48ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printPCRelOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printPCRelTLSOperand(const MCInst *MI, int OpNum, raw_ostream &O);
   void printAccessRegOperand(const MCInst *MI, int OpNum, raw_ostream &O);
 
   // Print the mnemonic for a condition-code mask ("ne", "lh", etc.)
   // This forms part of the instruction name rather than the operand list.
   void printCond4Operand(const MCInst *MI, int OpNum, raw_ostream &O);
 };
 } // end namespace llvm
 
 #endif

lib/Target/SystemZ/InstPrinter/SystemZInstPrinter.cpp

void SystemZInstPrinter::printS32ImmOperand(const MCInst *MI, int OpNum,
   printSImmOperand<32>(MI, OpNum, O);
 }
 
 void SystemZInstPrinter::printU32ImmOperand(const MCInst *MI, int OpNum,
                                             raw_ostream &O) {
   printUImmOperand<32>(MI, OpNum, O);
 }
 
+void SystemZInstPrinter::printU48ImmOperand(const MCInst *MI, int OpNum,
+                                            raw_ostream &O) {
+  printUImmOperand<48>(MI, OpNum, O);
+}
+
 void SystemZInstPrinter::printAccessRegOperand(const MCInst *MI, int OpNum,
                                                raw_ostream &O) {
   uint64_t Value = MI->getOperand(OpNum).getImm();
   assert(Value < 16 && "Invalid access register number");
   O << "%a" << (unsigned int)Value;
 }
 
 void SystemZInstPrinter::printPCRelOperand(const MCInst *MI, int OpNum,

lib/Target/SystemZ/SystemZInstrFormats.td

class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   let Inst{35-16} = XBD2;
   let Inst{15-12} = M3;
   let Inst{11}    = V1{4};
   let Inst{10-8}  = 0;
   let Inst{7-0}   = op{7-0};
 }
 
 //===----------------------------------------------------------------------===//
+// Instruction classes for .insn directives
+//===----------------------------------------------------------------------===//
+
+class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstE<0, outs, ins, asmstr, pattern> {
+  bits<16> enc;
+
+  let Inst = enc;
+}
+
+class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRI<0, outs, ins, asmstr, pattern> {
+  bits<32> enc;
+
+  let Inst{31-24} = enc{31-24};
+  let Inst{19-16} = enc{19-16};
+}
+
+class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRIEd<0, outs, ins, asmstr, pattern> {
+  bits<48> enc;
+
+  let Inst{47-40} = enc{47-40};
+  let Inst{7-0}   = enc{7-0};
+}
+
+class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRIL<0, outs, ins, asmstr, pattern> {
+  bits<48> enc;
+  string type;
+
+  let Inst{47-40} = enc{47-40};
+  let Inst{35-32} = enc{35-32};
+}
+
+class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRIS<0, outs, ins, asmstr, pattern> {
+  bits<48> enc;
+
+  let Inst{47-40} = enc{47-40};
+  let Inst{7-0}   = enc{7-0};
+}
+
+class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRR<0, outs, ins, asmstr, pattern> {
+  bits<16> enc;
+
+  let Inst{15-8} = enc{15-8};
+}
+
+class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRRE<0, outs, ins, asmstr, pattern> {
+  bits<32> enc;
+
+  let Inst{31-16} = enc{31-16};
+}
+
+class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRRF<0, outs, ins, asmstr, pattern> {
+  bits<32> enc;
+
+  let Inst{31-16} = enc{31-16};
+}
+
+class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRRS<0, outs, ins, asmstr, pattern> {
+  bits<48> enc;
+
+  let Inst{47-40} = enc{47-40};
+  let Inst{7-0}   = enc{7-0};
+}
+
+class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRS<0, outs, ins, asmstr, pattern> {
+  bits<32> enc;
+
+  let Inst{31-24} = enc{31-24};
+}
+
+// RSE is like RSY except with a 12 bit displacement (instead of 20).
+class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRSY<6, outs, ins, asmstr, pattern> {
+  bits <48> enc;
+
+  let Inst{47-40} = enc{47-40};
+  let Inst{31-16} = BD2{15-0};
+  let Inst{15-8}  = 0;
+  let Inst{7-0}   = enc{7-0};
+}
+
+class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRSI<0, outs, ins, asmstr, pattern> {
+  bits<32> enc;
+
+  let Inst{31-24} = enc{31-24};
+}
+
+class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRSY<0, outs, ins, asmstr, pattern> {
+  bits<48> enc;
+
+  let Inst{47-40} = enc{47-40};
+  let Inst{7-0}   = enc{7-0};
+}
+
+class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRX<0, outs, ins, asmstr, pattern> {
+  bits<32> enc;
+
+  let Inst{31-24} = enc{31-24};
+}
+
+class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRXE<0, outs, ins, asmstr, pattern> {
+  bits<48> enc;
+
+  let M3 = 0;
+
+  let Inst{47-40} = enc{47-40};
+  let Inst{7-0}   = enc{7-0};
+}
+
+class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRXF<0, outs, ins, asmstr, pattern> {
+  bits<48> enc;
+
+  let Inst{47-40} = enc{47-40};
+  let Inst{7-0}   = enc{7-0};
+}
+
+class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstRXY<0, outs, ins, asmstr, pattern> {
+  bits<48> enc;
+
+  let Inst{47-40} = enc{47-40};
+  let Inst{7-0}   = enc{7-0};
+}
+
+class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstS<0, outs, ins, asmstr, pattern> {
+  bits<32> enc;
+
+  let Inst{31-16} = enc{31-16};
+}
+
+class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSI<0, outs, ins, asmstr, pattern> {
+  bits<32> enc;
+
+  let Inst{31-24} = enc{31-24};
+}
+
+class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSIY<0, outs, ins, asmstr, pattern> {
+  bits<48> enc;
+
+  let Inst{47-40} = enc{47-40};
+  let Inst{7-0}   = enc{7-0};
+}
+
+class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSIL<0, outs, ins, asmstr, pattern> {
+  bits<48> enc;
+
+  let Inst{47-32} = enc{47-32};
+}
+
+class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSSd<0, outs, ins, asmstr, pattern> {
+  bits<48> enc;
+
+  let Inst{47-40} = enc{47-40};
+}
+
+class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSSE<0, outs, ins, asmstr, pattern> {
+  bits<48> enc;
+
+  let Inst{47-32} = enc{47-32};
+}
+
+class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSSF<0, outs, ins, asmstr, pattern> {
+  bits<48> enc;
+
+  let Inst{47-40} = enc{47-40};
+  let Inst{35-32} = enc{35-32};
+}
+
+//===----------------------------------------------------------------------===//
 // Instruction definitions with semantics
 //===----------------------------------------------------------------------===//
 //
 // These classes have the form [Cond]<Category><Format>, where <Format> is one
 // of the formats defined above and where <Category> describes the inputs
 // and outputs.  "Cond" is used if the instruction is conditional,
 // in which case the 4-bit condition-code mask is added as a final operand.
 // <Category> can be one of:

lib/Target/SystemZ/SystemZInstrInfo.td

def STRAG : InstSSE<0xE502, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
                       "strag\t$BD1, $BD2", []>;
 
 let Defs = [R0D, R1D], mayLoad = 1 in
   def ECTG : InstSSF<0xC81, (outs),
                             (ins bdaddr12only:$BD1, bdaddr12only:$BD2, GR64:$R3),
                      "ectg\t$BD1, $BD2, $R3", []>;
 
 //===----------------------------------------------------------------------===//
+// .insn directive instructions
+//===----------------------------------------------------------------------===//
+
+let isCodeGenOnly = 1 in {
+  def InsnE   : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>;
+  def InsnRI  : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1,
+                                             imm32sx16:$I2),
+                                ".insn ri,$enc,$R1,$I2", []>;
+  def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
+                                              AnyReg:$R3, brtarget16:$I2),
+                                 ".insn rie,$enc,$R1,$R3,$I2", []>;
+  def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
+                                              brtarget32:$I2),
+                                 ".insn ril,$enc,$R1,$I2", []>;
+  def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
+                                               uimm32:$I2),
+                                  ".insn rilu,$enc,$R1,$I2", []>;
+  def InsnRIS : DirectiveInsnRIS<(outs),
+                                 (ins imm64zx48:$enc, AnyReg:$R1,
+                                      imm32sx8:$I2, imm32zx4:$M3,
+                                      bdaddr12only:$BD4),
+                                 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>;
+  def InsnRR : DirectiveInsnRR<(outs),
+                               (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2),
+                               ".insn rr,$enc,$R1,$R2", []>;
+  def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc,
+                                              AnyReg:$R1, AnyReg:$R2),
+                                 ".insn rre,$enc,$R1,$R2", []>;
+  def InsnRRF : DirectiveInsnRRF<(outs),
+                                 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
+                                      AnyReg:$R3, imm32zx4:$R4),
+                                 ".insn rrf,$enc,$R1,$R2,$R3,$R4", []>;
+  def InsnRRS : DirectiveInsnRRS<(outs),
+                                 (ins imm64zx48:$enc, AnyReg:$R1,
+                                      AnyReg:$R2, imm32zx4:$M3,
+                                      bdaddr12only:$BD4),
+                                 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>;
+  def InsnRS  : DirectiveInsnRS<(outs),
+                                (ins imm64zx32:$enc, AnyReg:$R1,
+                                     AnyReg:$R3, bdaddr12only:$BD2),
+                                ".insn rs,$enc,$R1,$R3,$BD2", []>;
+  def InsnRSE : DirectiveInsnRSE<(outs),
+                                 (ins imm64zx48:$enc, AnyReg:$R1,
+                                      AnyReg:$R3, bdaddr12only:$BD2),
+                                 ".insn rse,$enc,$R1,$R3,$BD2", []>;
+  def InsnRSI : DirectiveInsnRSI<(outs),
+                                 (ins imm64zx48:$enc, AnyReg:$R1,
+                                      AnyReg:$R3, brtarget16:$RI2),
+                                 ".insn rsi,$enc,$R1,$R3,$RI2", []>;
+  def InsnRSY : DirectiveInsnRSY<(outs),
+                                 (ins imm64zx48:$enc, AnyReg:$R1,
+                                      AnyReg:$R3, bdaddr20only:$BD2),
+                                 ".insn rsy,$enc,$R1,$R3,$BD2", []>;
+  def InsnRX  : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1,
+                                             bdxaddr12only:$XBD2),
+                                ".insn rx,$enc,$R1,$XBD2", []>;
+  def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
+                                              bdxaddr12only:$XBD2),
+                                 ".insn rxe,$enc,$R1,$XBD2", []>;
+  def InsnRXF : DirectiveInsnRXF<(outs),
+                                 (ins imm64zx48:$enc, AnyReg:$R1,
+                                      AnyReg:$R3, bdxaddr12only:$XBD2),
+                                 ".insn rxf,$enc,$R1,$R3,$XBD2", []>;
+  def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
+                                              bdxaddr20only:$XBD2),
+                                 ".insn rxy,$enc,$R1,$XBD2", []>;
+  def InsnS : DirectiveInsnS<(outs),
+                             (ins imm64zx32:$enc, bdaddr12only:$BD2),
+                             ".insn s,$enc,$BD2", []>;
+  def InsnSI : DirectiveInsnSI<(outs),
+                               (ins imm64zx32:$enc, bdaddr12only:$BD1,
+                                    imm32sx8:$I2),
+                               ".insn si,$enc,$BD1,$I2", []>;
+  def InsnSIY : DirectiveInsnSIY<(outs),
+                                 (ins imm64zx48:$enc,
+                                      bdaddr20only:$BD1, imm32zx8:$I2),
+                                 ".insn siy,$enc,$BD1,$I2", []>;
+  def InsnSIL : DirectiveInsnSIL<(outs),
+                                 (ins imm64zx48:$enc, bdaddr12only:$BD1,
+                                      imm32zx16:$I2),
+                                 ".insn sil,$enc,$BD1,$I2", []>;
+  def InsnSS : DirectiveInsnSS<(outs),
+                               (ins imm64zx48:$enc, bdxaddr12only:$XBD1,
+                                    bdaddr12only:$BD2, AnyReg:$R3),
+                               ".insn ss,$enc,$XBD1,$BD2,$R3", []>;
+  def InsnSSE : DirectiveInsnSSE<(outs),
+                                 (ins imm64zx48:$enc,
+                                      bdaddr12only:$BD1,bdaddr12only:$BD2),
+                                 ".insn sse,$enc,$BD1,$BD2", []>;
+  def InsnSSF : DirectiveInsnSSF<(outs),
+                                 (ins imm64zx48:$enc, bdaddr12only:$BD1,
+                                      bdaddr12only:$BD2, AnyReg:$R3),
+                                 ".insn ssf,$enc,$BD1,$BD2,$R3", []>;
+}
+
+//===----------------------------------------------------------------------===//
 // Peepholes.
 //===----------------------------------------------------------------------===//
 
 // Use AL* for GR64 additions of unsigned 32-bit values.
 defm : ZXB<add, GR64, ALGFR>;
 def  : Pat<(add GR64:$src1, imm64zx32:$src2),
            (ALGFI GR64:$src1, imm64zx32:$src2)>;
 def  : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),

lib/Target/SystemZ/SystemZOperands.td

 }]>;
 
 // Truncate an immediate to a 32-bit unsigned quantity.
 def UIMM32 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), SDLoc(N),
                                    MVT::i64);
 }]>;
 
+// Truncate an immediate to a 48-bit unsigned quantity.
+def UIMM48 : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(uint64_t(N->getZExtValue()) & 0xffffffffffff,
+                                   SDLoc(N), MVT::i64);
+}]>;
+
 // Negate and then truncate an immediate to a 32-bit unsigned quantity.
 def NEGIMM32 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), SDLoc(N),
                                    MVT::i64);
 }]>;
 
 //===----------------------------------------------------------------------===//
 // Immediate asm operands.
 //===----------------------------------------------------------------------===//
 
 def U1Imm  : ImmediateAsmOperand<"U1Imm">;
 def U2Imm  : ImmediateAsmOperand<"U2Imm">;
 def U3Imm  : ImmediateAsmOperand<"U3Imm">;
 def U4Imm  : ImmediateAsmOperand<"U4Imm">;
 def U6Imm  : ImmediateAsmOperand<"U6Imm">;
 def S8Imm  : ImmediateAsmOperand<"S8Imm">;
 def U8Imm  : ImmediateAsmOperand<"U8Imm">;
 def U12Imm : ImmediateAsmOperand<"U12Imm">;
 def S16Imm : ImmediateAsmOperand<"S16Imm">;
 def U16Imm : ImmediateAsmOperand<"U16Imm">;
 def S32Imm : ImmediateAsmOperand<"S32Imm">;
 def U32Imm : ImmediateAsmOperand<"U32Imm">;
+def U48Imm : ImmediateAsmOperand<"U48Imm">;
 
 //===----------------------------------------------------------------------===//
 // i32 immediates
 //===----------------------------------------------------------------------===//
 
 // Immediates for the lower and upper 16 bits of an i32, with the other
 // bits of the i32 being zero.
 def imm32ll16 : Immediate<i32, [{

 def imm64zx32 : Immediate<i64, [{
   return isUInt<32>(N->getZExtValue());
 }], UIMM32, "U32Imm">;
 
 def imm64zx32n : Immediate<i64, [{
   return isUInt<32>(-N->getSExtValue());
 }], NEGIMM32, "U32Imm">;
 
+def imm64zx48 : Immediate<i64, [{
+  return isUInt<64>(N->getZExtValue());
+}], UIMM48, "U48Imm">;
+
 def imm64 : ImmLeaf<i64, [{}]>, Operand<i64>;
 
 //===----------------------------------------------------------------------===//
 // Floating-point immediates
 //===----------------------------------------------------------------------===//
 
 // Floating-point zero.
 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;

lib/Target/SystemZ/SystemZRegisterInfo.td

 // context evaluates as 0.
 defm ADDR32 : SystemZRegClass<"ADDR32", [i32], 32, (sub GR32Bit, R0L)>;
 defm ADDR64 : SystemZRegClass<"ADDR64", [i64], 64, (sub GR64Bit, R0D)>;
 
 // Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
 // of a GR128.
 defm ADDR128 : SystemZRegClass<"ADDR128", [untyped], 128, (sub GR128Bit, R0Q)>;
 
+// Any type register. Used for .insn directives when we don't know what the
+// register types could be.
+defm AnyReg : SystemZRegClass<"AnyReg",
+                              [i64, f64, v8i8, v4i16, v2i32, v2f32], 64,
+                              (add (sequence "R%uD", 0, 15),
+                                   (sequence "F%uD", 0, 15),
+                                   (sequence "V%u", 0, 15))>;
+
 //===----------------------------------------------------------------------===//
 // Floating-point registers
 //===----------------------------------------------------------------------===//
 
 // Maps FPR register numbers to their DWARF encoding.
 class DwarfMapping<int id> { int Id = id; }
 
 def F0Dwarf  : DwarfMapping<16>;

test/MC/SystemZ/directive-insn.s

+# RUN: llvm-mc -triple s390x-linux-gnu -filetype=obj %s | \
+# RUN: llvm-objdump -mcpu=zEC12 -disassemble - | FileCheck %s
+
+# Test the .insn directive which provides a way of encoding an instruction
+# directly. It takes a format, encoding, and operands based on the format.
+
+#CHECK: 01 01                 pr
+  .insn e,0x0101
+
+#CHECK: a7 18 12 34           lhi %r1, 4660
+  .insn ri,0xa7080000,%r1,0x1234
+
+# GAS considers this instruction's immediate operand to be PC relative.
+#CHECK: ec 12 00 06 00 76     crj %r1, %r2, 0, 0x12
+  .insn rie,0xec0000000076,%r1,%r2,12
+#CHECK: ec 12 00 03 00 64     cgrj %r1, %r2, 0, 0x12
+  .insn rie,0xec0000000064,%r1,%r2,label.rie
+#CHECK: label.rie:
+label.rie:
+
+# GAS considers this instruction's immediate operand to be PC relative.
+#CHECK: c6 1d 00 00 00 06     crl %r1, 0x1e
+  .insn ril,0xc60d00000000,%r1,12
+#CHECK: c6 18 00 00 00 03     cgrl %r1, 0x1e
+  .insn ril,0xc60800000000,%r1,label.ril
+#CHECK: label.ril:
+label.ril:
+
+#CHECK: c2 2b 80 00 00 00     alfi %r2, 2147483648
+  .insn rilu,0xc20b00000000,%r2,0x80000000
+
+#CHECK: ec 1c f0 a0 34 fc     cgible %r1, 52, 160(%r15)
+  .insn ris,0xec00000000fc,%r1,0x34,0xc,160(%r15)
+
+# Test using an integer in place of a register.
+#CHECK: 18 23                 lr %r2, %r3
+  .insn rr,0x1800,2,3
+
+#CHECK: b9 14 00 45           lgfr %r4, %r5
+  .insn rre,0xb9140000,%r4,%r5
+
+# Test FP and GR registers in a single directive.
+#CHECK: b3 c1 00 fe           ldgr %f15, %r14
+  .insn rre,0xb3c10000,%f15,%r14
+
+# Test using an integer in place of a register.
+#CHECK: b3 44 34 12           ledbra %f1, 3, %f2, 4
+  .insn rrf,0xb3440000,%f1,2,%f3,4
+
+#CHECK: ec 34 f0 b4 a0 e4     cgrbhe %r3, %r4, 180(%r15)
+  .insn rrs,0xec00000000e4,%r3,%r4,0xa,180(%r15)
+
+#CHECK: ba 01 f0 a0           cs %r0, %r1, 160(%r15)
+  .insn rs,0xba000000,%r0,%r1,160(%r15)
+
+# GAS considers this instruction's immediate operand to be PC relative.
+#CHECK: 84 13 00 04           brxh %r1, %r3, 0x4a
+  .insn rsi,0x84000000,%r1,%r3,8
+#CHECK: 84 13 00 02           brxh %r1, %r3, 0x4a
+  .insn rsi,0x84000000,%r1,%r3,label.rsi
+#CHECK: label.rsi:
+label.rsi:
+
+# RSE formats are short displacement versions of the RSY formats.
+#CHECK: eb 12 f0 a0 00 f8     laa %r1, %r2, 160(%r15)
+  .insn rse,0xeb00000000f8,%r1,%r2,160(%r15)
+
+#CHECK: eb 12 f3 45 12 30     csg %r1, %r2, 74565(%r15)
+  .insn rsy,0xeb0000000030,%r1,%r2,74565(%r15)
+
+#CHECK: 59 13 f0 a0           c %r1, 160(%r3,%r15)
+  .insn rx,0x59000000,%r1,160(%r3,%r15)
+
+#CHECK: ed 13 f0 a0 00 19     cdb %f1, 160(%r3,%r15)
+  .insn rxe,0xed0000000019,%f1,160(%r3,%r15)
+
+#CHECK: ed 23 f0 a0 10 1e     madb %f1, %f2, 160(%r3,%r15)
+  .insn rxf,0xed000000001e,%f1,%f2,160(%r3,%r15)
+
+#CHECK: ed 12 f1 23 90 65     ldy %f1, -458461(%r2,%r15)
+  .insn rxy,0xed0000000065,%f1,-458461(%r2,%r15)
+
+#CHECK: b2 fc f0 a0           tabort 160(%r15)
+  .insn s,0xb2fc0000,160(%r15)
+
+#CHECK: 91 34 f0 a0           tm 160(%r15), 52
+  .insn si,0x91000000,160(%r15),52
+
+#CHECK: eb f0 fc de ab 51     tmy -344866(%r15), 240
+  .insn siy,0xeb0000000051,-344866(%r15),240
+
+#CHECK: e5 60 f0 a0 12 34     tbegin 160(%r15), 4660
+  .insn sil,0xe56000000000,160(%r15),0x1234
+
+#CHECK: d9 13 f1 23 e4 56     mvck 291(%r1,%r15), 1110(%r14), %r3
+  .insn ss,0xd90000000000,291(%r1,%r15),1110(%r14),%r3
+
+#CHECK: e5 02 10 a0 21 23     strag 160(%r1), 291(%r2)
+  .insn sse,0xe50200000000,160(%r1),291(%r2)
+
+#CHECK: c8 31 f0 a0 e2 34     ectg 160(%r15), 564(%r14), %r3
+  .insn ssf,0xc80100000000,160(%r15),564(%r14),%r3