[inlineasm] Propagate operand constraints to the backend

[sdardis]

Summary

When SelectionDAGISel transforms a node representing an inline asm
block, memory constraint information is not preserved. This can cause
constraints to be broken when a memory offset is of the form:

offset + frame index

when the frame is resolved.

By propagating the constraints all the way to the backend, targets can
enforce memory operands of inline assembly to conform to their constraints.

For MIPSR6, some instructions had their offsets reduced to 9 bits from
16 bits such as ll/sc. This becomes problematic when using inline assembly
to perform atomic operations, as an offset can generated that is too big to
encode in the instruction.

[dsanders]

This patch is going in the right direction but I think there's a couple extra things we ought to do to round this off:

• Stop MachineInstr::print() from printing register constraints when the flag do not hold a register constraint.
• Make MachineInstr::print() print the memory constraint when the flags have one.
• Add assertions to InlineAsm::getFlagWordForRegClass() and Inline::getFlagWordForMem() to make sure we cannot put the wrong kind of constraint in the relevant flag bits.

I also think the summary needs to mention that frameindex nodes introduce the out of range offsets that are causing the problem. Without the frameindex nodes we would have dealt with the out-of-range offsets during isel.

lib/Target/Mips/MipsSERegisterInfo.cpp

66–93

I don't mind if we do this in a separate patch but we need to cover the various versions of the LL/SC instructions in this switch statement too.

68

Scoping nit: Please move this into the 'case Mips::INLINE_ASM:', adding the necessary braces to allow this.

86

This value depends on the ISA. It should be 9-bit for MIPS32R6/MIPS64R6 and 16-bit for earlier ISA's.

179

This is over 80 columns

test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll

1–2

Please add a pre-R6 test to prove that 9-16 bit offsets are still accepted by the inline assembly for this case.

14–17

For the R6 case, could you check for the addiu too?

[sdardis]

Updated as per review comments, retitled and new summary.

[dsanders]

LGTM with the pre-R6 test and the addiu check

test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll

3–4

This hasn't been done

16–19

This hasn't been done.

[sdardis]

Thanks, committed rL275786.

lib/CodeGen/MachineInstr.cpp

MachineInstr::getRegClassConstraint(unsigned OpIdx,
 
   // Inline asm stores register class constraints in the flag word.
   int FlagIdx = findInlineAsmFlagIdx(OpIdx);
   if (FlagIdx < 0)
     return nullptr;
 
   unsigned Flag = getOperand(FlagIdx).getImm();
   unsigned RCID;
-  if (InlineAsm::hasRegClassConstraint(Flag, RCID))
+  if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
+       InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
+       InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
+      InlineAsm::hasRegClassConstraint(Flag, RCID))
     return TRI->getRegClass(RCID);
 
   // Assume that all registers in a memory operand are pointers.
   if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
     return TRI->getPointerRegClass(MF);
 
   return nullptr;
 }

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

if (!InlineAsm::isMemKind(Flags)) {
         for (; TiedToOperand; --TiedToOperand) {
           CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
           Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
         }
       }
 
       // Otherwise, this is a memory operand.  Ask the target to select it.
       std::vector<SDValue> SelOps;
-      if (SelectInlineAsmMemoryOperand(InOps[i+1],
-                                       InlineAsm::getMemoryConstraintID(Flags),
-                                       SelOps))
+      unsigned ConstraintID = InlineAsm::getMemoryConstraintID(Flags);
+      if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
         report_fatal_error("Could not match memory address.  Inline asm"
                            " failure!");
 
       // Add this to the output node.
       unsigned NewFlags =
         InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
+      NewFlags = InlineAsm::getFlagWordForMem(NewFlags, ConstraintID);
       Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32));
       Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
       i += 2;
     }
   }
 
   // Add the glue input back if present.
   if (e != InOps.size())

lib/Target/Mips/MipsSERegisterInfo.cpp

 MipsSERegisterInfo::intRegClass(unsigned Size) const {
   if (Size == 4)
     return &Mips::GPR32RegClass;
 
   assert(Size == 8);
   return &Mips::GPR64RegClass;
 }
 
-/// Get the size of the offset supported by the given load/store.
+/// Get the size of the offset supported by the given load/store/inline asm.
 /// The result includes the effects of any scale factors applied to the
 /// instruction immediate.
-static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode) {
+static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode,
+                                                    MachineOperand MO) {
+  unsigned ConstraintID;
   switch (Opcode) {
   case Mips::LD_B:
   case Mips::ST_B:
     return 10;
   case Mips::LD_H:
   case Mips::ST_H:
     return 10 + 1 /* scale factor */;
   case Mips::LD_W:
   case Mips::ST_W:
     return 10 + 2 /* scale factor */;
   case Mips::LD_D:
   case Mips::ST_D:
     return 10 + 3 /* scale factor */;
+  case Mips::INLINEASM:
+    ConstraintID  = InlineAsm::getMemoryConstraintID(MO.getImm());
+    switch (ConstraintID) {
+      case InlineAsm::Constraint_ZC:
+        return 9;
+      default:
+        return 16;
+    }
   default:
     return 16;
   }
 }
 
 /// Get the scale factor applied to the immediate in the given load/store.
 static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
   switch (Opcode) {
   case Mips::LD_H:
   case Mips::ST_H:
     return 2;
   case Mips::LD_W:
void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
   Offset += MI.getOperand(OpNo + 1).getImm();
 
   DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
 
   if (!MI.isDebugValue()) {
     // Make sure Offset fits within the field available.
     // For MSA instructions, this is a 10-bit signed immediate (scaled by
     // element size), otherwise it is a 16-bit signed immediate.
-    unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode());
+    unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode(), MI.getOperand(OpNo-1));
     unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode());
 
     if (OffsetBitSize < 16 && isInt<16>(Offset) &&
         (!isIntN(OffsetBitSize, Offset) ||
          OffsetToAlignment(Offset, OffsetAlign) != 0)) {
       // If we have an offset that needs to fit into a signed n-bit immediate
       // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
       MachineBasicBlock &MBB = *MI.getParent();

test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll

+; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips64r6 < %s | FileCheck %s
+
+%struct.anon = type { [63 x i32], i32, i32 }
+
+define i32 @Atomic() {
+; CHECK-LABEL: Atomic:
+entry:
+  %s = alloca %struct.anon, align 4
+  %0 = bitcast %struct.anon* %s to i8*
+  %count = getelementptr inbounds %struct.anon, %struct.anon* %s, i64 0, i32 1
+  store i32 0, i32* %count, align 4
+
+; CHECK: #APP
+; CHECK: ll ${{[0-9]+}}, 0(${{[0-9a-z]+}})
+; CHECK: sc ${{[0-9]+}}, 0(${{[0-9a-z]+}})
+; CHECK: #NO_APP
+
+  %1 = call { i32, i32 } asm sideeffect ".set push\0A.set noreorder\0A1:\0All $0, $2\0Aaddu $1, $0, $3\0Asc $1, $2\0Abeqz $1, 1b\0Aaddu $1, $0, $3\0A.set pop\0A", "=&r,=&r,=*^ZC,Ir,*^ZC,~{memory},~{$1}"(i32* %count, i32 10, i32* %count)
+  %asmresult1.i = extractvalue { i32, i32 } %1, 1
+  %cmp = icmp ne i32 %asmresult1.i, 10
+  %conv = zext i1 %cmp to i32
+  %call2 = call i32 @f(i32 signext %conv)
+  ret i32 %call2
+}
+
+declare i32 @f(i32 signext)