[mips] Enable tail calls by default

[sdardis]

Summary

Enable tail calls by default for (micro)MIPS(64).

microMIPS is slightly more tricky than doing it for MIPS(R6) or microMIPSR6.
microMIPS has two instruction encodings: 16bit and 32bit along with some
restrictions on the size of the instruction that can fill the delay slot.
For safe tail calls for microMIPS, the delay slot filler attempts to find
a correct size instruction for the delay slot of TAILCALL pseudos.

[sdardis]

Changed TailCallReg (all variants) to use jr $dst over jalr zero, $dst. This should avoid mispredicts on implementations with a return address predictor.

[sdardis]

Ping.

[dsanders]

Most of my comments are nits. The important one is the accidental removal of predicates on the new instructions with a 'let Predicates = ...' statement.

lib/Target/Mips/MicroMipsInstrInfo.td

490 ↗

(On Diff #61531)

indentation

993–995 ↗

(On Diff #61531)

This doesn't have the predicates you expect because the 'let Predicates = ...' statement discards all the predicates and replaces them with the 1-element list '[InMicroMips]'. The effects of ISA_MIPS1_NOT_32R6_64R6 are lost.

Changing Predicates to AdditionalPredicates should fix this for now but we need to move InMicroMips to another sublist of PredicateControl in the future.

The other instances should be fixed too but that's for another patch

lib/Target/Mips/MipsDelaySlotFiller.cpp

561 ↗

(On Diff #60040)

Indentation

617–622 ↗

(On Diff #60040)

becuase -> because

Also, the sentence starting 'This would save 16 bits ...' seems to be missing some words.

709–713 ↗

(On Diff #60040)

I see that 'j' is the tailcall instruction at the moment. I agree that it's fairly safe to rely on this instruction since it has a 256MB range but it's important to mention that this range isn't centered on the instruction like a normal PC-relative instruction. It's technically possible for small offsets like +/-4 to be out of range. JAL has the same issue so I think this is a problem that can be addressed later.

Also, a couple nits:

• Could you clarify that the '32bit' is the opcode size and not the range?
• ranage -> range.

lib/Target/Mips/MipsSEISelLowering.cpp

30–31 ↗

(On Diff #61531)

I think we should drop the 'enable' and 'disable' (maybe have 'Use' instead) and just have:

static cl::opt<bool>
MipsTailCalls("mips-tail-calls", cl::Hidden,
              cl::desc("MIPS: Disable tail calls."), cl::init(true));

That way we control the default with cl::init and override it with -mips-tail-calls=false

test/CodeGen/Mips/compactbranches/tailrecursion.ll

23 ↗

(On Diff #61531)

This matches the first 'f' in the file (e.g. .file) rather than the label 'f' at the start of the function. It needs a ':'

33 ↗

(On Diff #61531)

menomic -> mnemonic

test/CodeGen/Mips/i64arg.ll

5–25 ↗

(On Diff #61531)

We shouldn't need to switch the R2/R3 variables over since CHECK-DAG takes care of ordering differences.

[sdardis]

Update as per review comments.

I will see about changing the usage of branch instead of jump instructions in a later patch.

[sdardis]

Missed the necessary -target-abi n64 option on some of the tests.

[sdardis]

Rebase, ping.

[sdardis]

Ping.

[dsanders]

LGTM

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

class JumpRegCMM16<string opstr, RegisterOperand RO> :
   MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
                   [], II_JRC, FrmR> {
   let isTerminator = 1;
   let isBarrier = 1;
   let isBranch = 1;
   let isIndirectBranch = 1;
 }
 
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
+    hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in {
+  class TailCall_MM<Instruction JumpInst> :
+    PseudoSE<(outs), (ins calltarget:$target), [], II_J>,
+    PseudoInstExpansion<(JumpInst jmptarget_mm:$target)>;
+
+  class TailCallReg_MM<RegisterOperand RO, Instruction JRInst,
+                       RegisterOperand ResRO = RO> :
+    PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
+    PseudoInstExpansion<(JRInst ResRO:$rs)>;
+}
+
 // Break16 and Sdbbp16
 class BrkSdbbp16MM<string opstr> :
   MicroMipsInst16<(outs), (ins uimm4:$code_),
                   !strconcat(opstr, "\t$code_"),
                   [], NoItinerary, FrmOther>;
 
 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
   MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
   def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
   def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
 
   def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10>, SDBBP_FM_MM;
 
   def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
 }
 
+let AdditionalPredicates = [InMicroMips] in {
+  def TAILCALL_MM : TailCall_MM<J_MM>, ISA_MIPS1_NOT_32R6_64R6;
+  def TAILCALLREG_MM : TailCallReg_MM<GPR32Opnd, JR_MM>,
+                       ISA_MIPS1_NOT_32R6_64R6;
+}
+
 let DecoderNamespace = "MicroMips" in {
   def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,
                  RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;
   def LWU_MM : MMRel, LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU,
                              mem_simm12>, LL_FM_MM<0xe>,
                ISA_MICROMIPS32_NOT_MIPS32R6;
 }
 

llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td

def SELNEZ_D : R6MMR6Rel, SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6,
                  HARDFLOAT;
   def SELNEZ_S : R6MMR6Rel, SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6,
                  HARDFLOAT;
   def SEL_D : R6MMR6Rel, SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
   def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
 }
+def TAILCALL_R6 : TailCall<J>, ISA_MIPS32R6;
+def TAILCALLREG_R6 : TailCallReg<GPR32Opnd, JR>, GPR_32, ISA_MIPS32R6;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Aliases
 //
 //===----------------------------------------------------------------------===//
 
 let AdditionalPredicates = [NotInMicroMips] in {

llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
 
 let AdditionalPredicates = [NotInMicroMips],
     DecoderNamespace = "Mips32_64_PTR64" in {
 def LL64 : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_64,
            ISA_MIPS2_NOT_32R6_64R6;
 def SC64 : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_64,
            ISA_MIPS2_NOT_32R6_64R6;
+def JR64   : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>, PTR_64;
 }
 
+def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
+
 /// Jump and Branch Instructions
 let isCodeGenOnly = 1 in {
-  def JR64   : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
   def BEQ64  : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
   def BNE64  : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
   def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
   def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
   def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
   def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
-  def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
   def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
-  def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
+  def TAILCALLREG64 : TailCallReg<GPR64Opnd, JR64>, GPR_64, ISA_MIPS1_NOT_32R6_64R6;
 }
 
+
 def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>;
 def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>;
 
 /// Multiply and Divide Instructions.
 let AdditionalPredicates = [NotInMicroMips] in {
   def DMULT  : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
                MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
   def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,

llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td

 def BNEC64 : BNEC_ENC, BNEC64_DESC, ISA_MIPS64R6, GPR_64;
 def BNEZC64 : BNEZC_ENC, BNEZC64_DESC, ISA_MIPS64R6, GPR_64;
 }
 let DecoderNamespace = "Mips32r6_64r6_BranchZero" in {
 def BLTZC64 : BLTZC_ENC, BLTZC64_DESC, ISA_MIPS64R6, GPR_64;
 def BGEZC64 : BGEZC_ENC, BGEZC64_DESC, ISA_MIPS64R6, GPR_64;
 }
 
+def TAILCALL64_R6 : TailCall<J>, ISA_MIPS64R6;
+def TAILCALLREG64_R6 : TailCallReg<GPR64Opnd, JR64>, GPR_64,
+                       ISA_MIPS64R6;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Aliases
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
 

llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp

Iter Filler::replaceWithCompactBranch(MachineBasicBlock &MBB, Iter Branch,
   Branch = TII->genInstrWithNewOpc(NewOpcode, Branch);
 
   std::next(Branch)->eraseFromParent();
   return Branch;
 }
 
 // For given opcode returns opcode of corresponding instruction with short
 // delay slot.
+// For the pseudo TAILCALL*_MM instrunctions return the short delay slot
+// form. Unfortunately, TAILCALL<->b16 is denied as b16 has a limited range
+// that is too short to make use of for tail calls.
 static int getEquivalentCallShort(int Opcode) {
   switch (Opcode) {
   case Mips::BGEZAL:
     return Mips::BGEZALS_MM;
   case Mips::BLTZAL:
     return Mips::BLTZALS_MM;
   case Mips::JAL:
     return Mips::JALS_MM;
   case Mips::JALR:
     return Mips::JALRS_MM;
   case Mips::JALR16_MM:
     return Mips::JALRS16_MM;
+  case Mips::TAILCALL_MM:
+    llvm_unreachable("Attempting to shorten the TAILCALL_MM pseudo!");
+  case Mips::TAILCALLREG_MM:
+    return Mips::JR16_MM;
   default:
     llvm_unreachable("Unexpected call instruction for microMIPS.");
   }
 }
 
 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
 /// We assume there is only one delay slot per delayed instruction.
 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
       if (Filled) {
         // Get instruction with delay slot.
         MachineBasicBlock::instr_iterator DSI = I.getInstrIterator();
 
         if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 &&
             DSI->isCall()) {
           // If instruction in delay slot is 16b change opcode to
           // corresponding instruction with short delay slot.
+
+          // TODO: Implement an instruction mapping table of 16bit opcodes to
+          // 32bit opcodes so that an instruction can be expanded. This would
+          // save 16 bits as a TAILCALL_MM pseudo requires a fullsized nop.
+          // TODO: Permit b16 when branching backwards to the the same function
+          // if it is in range.
           DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode())));
         }
         continue;
       }
     }
 
     // For microMIPS if instruction is BEQ or BNE with one ZERO register, then
     // instead of adding NOP replace this instruction with the corresponding
if (STI.isTargetNaCl()) {
            baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||
           CurrI->modifiesRegister(Mips::SP, STI.getRegisterInfo()))
         continue;
     }
 
     bool InMicroMipsMode = STI.inMicroMipsMode();
     const MipsInstrInfo *TII = STI.getInstrInfo();
     unsigned Opcode = (*Slot).getOpcode();
+    // This is complicated by the tail call optimization. For non-PIC code
+    // there is only a 32bit sized unconditional branch which can be assumed
+    // to be able to reach the target. b16 only has a range of +/- 1 KB.
+    // It's entirely possible that the target function is reachable with b16
+    // but we don't have enough information to make that decision.
      if (InMicroMipsMode && TII->getInstSizeInBytes(*CurrI) == 2 &&
         (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch ||
-         Opcode == Mips::PseudoReturn))
+         Opcode == Mips::PseudoReturn || Opcode == Mips::TAILCALL))
       continue;
 
     Filler = CurrI;
     return true;
   }
 
   return false;
 }

llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp

// of the operands is zero.
       if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
         canUseShortMicroMipsCTI = true;
       break;
     // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
     // expanded to JR_MM, so they can be replaced with JRC16_MM.
     case Mips::JR:
     case Mips::PseudoReturn:
     case Mips::PseudoIndirectBranch:
+    case Mips::TAILCALLREG_MM:
       canUseShortMicroMipsCTI = true;
       break;
     }
   }
 
   // MIPSR6 forbids both operands being the zero register.
   if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
       (I->getOperand(0).isReg() &&
case Mips::BLTZ64:
       return Mips::BLTZC64;
     case Mips::BLEZ64:
       return Mips::BLEZC64;
     // For MIPSR6, the instruction 'jic' can be used for these cases. Some
     // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
     case Mips::JR:
     case Mips::PseudoReturn:
     case Mips::PseudoIndirectBranch:
+    case Mips::TAILCALLREG_MM:
+    case Mips::TAILCALLREG_R6:
       if (canUseShortMicroMipsCTI)
         return Mips::JRC16_MM;
       return Mips::JIC;
     case Mips::JALRPseudo:
       return Mips::JIALC;
     case Mips::JR64:
     case Mips::PseudoReturn64:
     case Mips::PseudoIndirectBranch64:
+    case Mips::TAILCALLREG64_R6:
       return Mips::JIC64;
     case Mips::JALR64Pseudo:
       return Mips::JIALC64;
     default:
       return 0;
     }
   }
 

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
              ISA_MIPS1_NOT_32R6_64R6;
 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
               BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
              ISA_MIPS1_NOT_32R6_64R6;
 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
               BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
-def TAILCALL : TailCall<J>;
-def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
+
+let AdditionalPredicates = [NotInMicroMips] in {
+def TAILCALL : TailCall<J>, ISA_MIPS1_NOT_32R6_64R6;
+def TAILCALLREG : TailCallReg<GPR32Opnd, JR>, ISA_MIPS1_NOT_32R6_64R6, GPR_32;
+}
 
 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
 class PseudoIndirectBranchBase<RegisterOperand RO> :
     MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
                II_IndirectBranchPseudo> {
   let isTerminator=1;
   let isBarrier=1;

llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp

 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetInstrInfo.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "mips-isel"
 
 static cl::opt<bool>
-EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
-                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
+UseMipsTailCalls("mips-tail-calls", cl::Hidden,
+                    cl::desc("MIPS: permit tail calls."), cl::init(true));
 
 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
                                    cl::desc("Expand double precision loads and "
                                             "stores to their single precision "
                                             "counterparts"));
 
 MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
                                            const MipsSubtarget &STI)
MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   case Mips::FEXP2_D_1_PSEUDO:
     return emitFEXP2_D_1(MI, BB);
   }
 }
 
 bool MipsSETargetLowering::isEligibleForTailCallOptimization(
     const CCState &CCInfo, unsigned NextStackOffset,
     const MipsFunctionInfo &FI) const {
-  if (!EnableMipsTailCalls)
+  if (!UseMipsTailCalls)
     return false;
 
   // Exception has to be cleared with eret.
   if (FI.isISR())
     return false;
 
   // Return false if either the callee or caller has a byval argument.
   if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())

llvm/trunk/test/CodeGen/Mips/biggot.ll

 ; RUN: llc -march=mipsel -mxgot -relocation-model=pic < %s | FileCheck %s -check-prefix=O32
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+n64 -mxgot -relocation-model=pic < %s | \
+; RUN: llc -march=mips64el -mcpu=mips64r2 -mxgot -relocation-model=pic < %s | \
 ; RUN: FileCheck %s -check-prefix=N64
 
 @v0 = external global i32
 
 define void @foo1() nounwind {
 entry:
+; O32-LABEL: foo1:
 ; O32: lui $[[R0:[0-9]+]], %got_hi(v0)
 ; O32: addu  $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}}
 ; O32: lw  ${{[0-9]+}}, %got_lo(v0)($[[R1]])
 ; O32: lui $[[R2:[0-9]+]], %call_hi(foo0)
 ; O32: addu  $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
 ; O32: lw  ${{[0-9]+}}, %call_lo(foo0)($[[R3]])
 
+; N64-LABEL: foo1:
 ; N64: lui $[[R0:[0-9]+]], %got_hi(v0)
 ; N64: daddu  $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}}
-; N64: ld  ${{[0-9]+}}, %got_lo(v0)($[[R1]])
 ; N64: lui $[[R2:[0-9]+]], %call_hi(foo0)
 ; N64: daddu  $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
+; N64: ld  ${{[0-9]+}}, %got_lo(v0)($[[R1]])
 ; N64: ld  ${{[0-9]+}}, %call_lo(foo0)($[[R3]])
 
   %0 = load i32, i32* @v0, align 4
   tail call void @foo0(i32 %0) nounwind
   ret void
 }
 
 declare void @foo0(i32)

llvm/trunk/test/CodeGen/Mips/brdelayslot.ll

 ; Default-NOT: nop
 ; Default:     .end
 ; None: jalr
 ; None: nop
 ; None: jr
 ; None: nop
 ; None: .end
 
-  tail call void @foo2(i32 3) nounwind
+  call void @foo2(i32 3) nounwind
   ret void
 }
 
 declare void @foo2(i32)
 
 ; Check that cvt.d.w goes into jalr's delay slot.
 ;
 define void @foo3(i32 %a) nounwind {
 entry:
 ; Default-LABEL:     foo3:
 ; Default:     jalr
 ; Default:     cvt.d.w
 
   %conv = sitofp i32 %a to double
-  tail call void @foo4(double %conv) nounwind
+  call void @foo4(double %conv) nounwind
   ret void
 }
 
 declare void @foo4(double)
 
 @g2 = external global i32
 @g1 = external global i32
 @g3 = external global i32

 ; Check that delay slot filler can place mov.s or mov.d in delay slot.
 ;
 ; Default-LABEL:     foo6:
 ; Default-NOT: nop
 ; Default:     .end foo6
 
 define void @foo6(float %a0, double %a1) nounwind {
 entry:
-  tail call void @foo7(double %a1, float %a0) nounwind
+  call void @foo7(double %a1, float %a0) nounwind
   ret void
 }
 
 declare void @foo7(double, float)
 
 ; Check that a store can move past other memory instructions.
 ;
 ; STATICO1-LABEL:      foo8:
 ; STATICO1:      jalr ${{[0-9]+}}
 ; STATICO1-NEXT: sw ${{[0-9]+}}, %lo(g1)
 
 @foo9 = common global void ()* null, align 4
 
 define i32 @foo8(i32 %a) nounwind {
 entry:
   store i32 %a, i32* @g1, align 4
   %0 = load void ()*, void ()** @foo9, align 4
-  tail call void %0() nounwind
+  call void %0() nounwind
   %1 = load i32, i32* @g1, align 4
   %add = add nsw i32 %1, %a
   ret i32 %add
 }
 
 ; Test searchForward. Check that the second jal's slot is filled with another
 ; instruction in the same block.
 ;

llvm/trunk/test/CodeGen/Mips/cconv/reserved-space.ll

 
 ; Test that O32 correctly reserved space for the four arguments, even when
 ; there aren't any as per section 5 of MD00305 (MIPS ABIs Described).
 
 declare void @foo() nounwind;
 
 define void @reserved_space() nounwind {
 entry:
-        tail call void @foo()
+        call void @foo()
         ret void
 }
 
 ; ALL-LABEL: reserved_space:
 ; O32:           addiu $sp, $sp, -24
 ; O32:           sw $ra, 20($sp)
 ; O32:           lw $ra, 20($sp)
 ; O32:           addiu $sp, $sp, 24

llvm/trunk/test/CodeGen/Mips/fastcc.ll

 ; NOODDSPREG-DAG:    lwc1    $f8, 16($[[R0]])
 ; NOODDSPREG-DAG:    lwc1    $f10, 20($[[R0]])
 ; NOODDSPREG-DAG:    lwc1    $f12, 24($[[R0]])
 ; NOODDSPREG-DAG:    lwc1    $f14, 28($[[R0]])
 ; NOODDSPREG-DAG:    lwc1    $f16, 32($[[R0]])
 ; NOODDSPREG-DAG:    lwc1    $f18, 36($[[R0]])
 
 ; NOODDSPREG-DAG:    lwc1    $[[F0:f[0-9]*[02468]]], 40($[[R0]])
-; NOODDSPREG-DAG:    swc1    $[[F0]], 0($sp)
+; NOODDSPREG-DAG:    swc1    $[[F0]], 8($sp)
 
   %0 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 0), align 4
   %1 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 1), align 4
   %2 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 2), align 4
   %3 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 3), align 4
   %4 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 4), align 4
   %5 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 5), align 4
   %6 = load float, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 6), align 4

llvm/trunk/test/CodeGen/Mips/gpreg-lazy-binding.ll

 ; RUN: llc -march=mipsel -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck %s
 
 @g = external global i32
 
 ; CHECK:     move  $gp
 ; CHECK:     jalr  $25
 ; CHECK:     nop
 ; CHECK-NOT: move  $gp
-; CHECK:     jalr  $25
+; CHECK:     jr    $25
 
 define void @f0() nounwind {
 entry:
   tail call void @externalFunc() nounwind
   tail call fastcc void @internalFunc()
   ret void
 }
 

llvm/trunk/test/CodeGen/Mips/i64arg.ll

 ; RUN: llc -march=mips -relocation-model=pic < %s | FileCheck %s
 
 define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind {
 entry:
-; CHECK-DAG: lw $[[R2:[0-9]+]], 80($sp)
-; CHECK-DAG: lw $[[R3:[0-9]+]], 84($sp)
+; CHECK-DAG: lw $[[R2:[0-9]+]], 64($sp)
+; CHECK-DAG: lw $[[R3:[0-9]+]], 68($sp)
 ; CHECK-DAG: move $[[R1:[0-9]+]], $5
 ; CHECK-DAG: move $[[R0:[0-9]+]], $4
 ; CHECK-DAG: ori $6, ${{[0-9]+}}, 3855
 ; CHECK-DAG: ori $7, ${{[0-9]+}}, 22136
 ; CHECK-DAG: lw  $25, %call16(ff1)
-; CHECK: jalr
+; CHECK: jalr $25
   tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind
 ; CHECK-DAG: lw $25, %call16(ff2)
 ; CHECK-DAG: move $4, $[[R2]]
 ; CHECK-DAG: move $5, $[[R3]]
 ; CHECK: jalr $25
   tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind
   %sub = add nsw i32 %i, -1
 ; CHECK-DAG: lw $25, %call16(ff3)
-; CHECK-DAG: sw $[[R1]], 28($sp)
-; CHECK-DAG: sw $[[R0]], 24($sp)
+; CHECK-DAG: sw $[[R1]], 76($sp)
+; CHECK-DAG: sw $[[R0]], 72($sp)
 ; CHECK-DAG: move $6, $[[R2]]
 ; CHECK-DAG: move $7, $[[R3]]
-; CHECK:     jalr $25
+; CHECK:     jr $25
   tail call void @ff3(i32 %i, i64 %ll, i32 %sub, i64 %ll1) nounwind
   ret void
 }
 
 declare void @ff1(i32, i64)
 
 declare void @ff2(i64, double)
 
 declare void @ff3(i32, i64, i32, i64)

llvm/trunk/test/CodeGen/Mips/indirectcall.ll

 ; RUN: llc  < %s -march=mipsel -relocation-model=static | FileCheck %s 
 
 define void @foo0(void (i32)* nocapture %f1) nounwind {
 entry:
-; CHECK: jalr $25
+; CHECK: jr $25
   tail call void %f1(i32 13) nounwind
   ret void
 }

llvm/trunk/test/CodeGen/Mips/lazy-binding.ll

 declare void @foo2()
 
 ; CHECK-LABEL: foo1:
 ; CHECK: lw $25, %call16(foo2)(${{[0-9]+}})
 ; CHECK: jalr $25
 ; CHECK: lw $25, %call16(foo2)(${{[0-9]+}})
 ; CHECK: jalr $25
 ; CHECK: lw $25, %call16(foo2)(${{[0-9]+}})
-; CHECK: jalr $25
+; CHECK: jr $25
 
 define void @foo1() {
 entry:
   tail call void @foo2()
   tail call void @foo2()
   tail call void @foo2()
   ret void
 }

llvm/trunk/test/CodeGen/Mips/llvm-ir/call.ll

 ; Test the 'call' instruction and the tailcall variant.
 
-; FIXME: We should remove the need for -enable-mips-tail-calls
-; RUN: llc -march=mips   -mcpu=mips32   -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
-; RUN: llc -march=mips   -mcpu=mips32r2 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
-; RUN: llc -march=mips   -mcpu=mips32r3 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
-; RUN: llc -march=mips   -mcpu=mips32r5 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
-; RUN: llc -march=mips   -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,R6C
-; RUN: llc -march=mips   -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,R6C
-; RUN: llc -march=mips64 -mcpu=mips4    -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64   -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r6 -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,R6C
+; RUN: llc -march=mips   -mcpu=mips32   -relocation-model=pic  < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r2 -relocation-model=pic  < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r3 -relocation-model=pic  < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r5 -relocation-model=pic  < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler  < %s | FileCheck %s -check-prefixes=ALL,O32,R6C
+; RUN: llc -march=mips   -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler  < %s | FileCheck %s -check-prefixes=ALL,O32,R6C
+; RUN: llc -march=mips64 -mcpu=mips4     < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64    < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r2  < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r3  < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r5  < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r6 -disable-mips-delay-filler  < %s | FileCheck %s -check-prefixes=ALL,N64,R6C
+; RUN: llc -march=mips   -mcpu=mips32   -relocation-model=pic  < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r2 -relocation-model=pic  < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r3 -relocation-model=pic  < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r5 -relocation-model=pic  < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -march=mips   -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler  < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
+; RUN: llc -march=mips   -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler  < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
+; RUN: llc -march=mips64 -mcpu=mips4     < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64    < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r2  < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r3  < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r5  < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -march=mips64 -mcpu=mips64r6 -disable-mips-delay-filler  < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=R6C
 
 declare void @extern_void_void()
 declare i32 @extern_i32_void()
 declare float @extern_float_void()
 
 define i32 @call_void_void() {
 ; ALL-LABEL: call_void_void:
 

 
 define void @musttail_call_void_void() {
 ; ALL-LABEL: musttail_call_void_void:
 
 ; O32:           lw $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
 
-; ALL:           jr $[[TGT]]
+; NOT-R6C:       jr   $[[TGT]]
+; R6C:           jrc  $[[TGT]]
 
   musttail call void @extern_void_void()
   ret void
 }
 
 define i32 @musttail_call_i32_void() {
 ; ALL-LABEL: musttail_call_i32_void:
 
 ; O32:           lw $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
 
-; ALL:           jr $[[TGT]]
+; NOT-R6C:       jr   $[[TGT]]
+; R6C:           jrc  $[[TGT]]
 
   %1 = musttail call i32 @extern_i32_void()
   ret i32 %1
 }
 
 define float @musttail_call_float_void() {
 ; ALL-LABEL: musttail_call_float_void:
 
 ; O32:           lw $[[TGT:[0-9]+]], %call16(extern_float_void)($gp)
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp)
 
-; ALL:           jr $[[TGT]]
+; NOT-R6C:       jr   $[[TGT]]
+; R6C:           jrc  $[[TGT]]
 
   %1 = musttail call float @extern_float_void()
   ret float %1
 }
 
 define i32 @indirect_call_void_void(void ()* %addr) {
 ; ALL-LABEL: indirect_call_void_void:
 

 }
 
 ; We can't use 'musttail' here because the verifier is too conservative and
 ; prohibits any prototype difference.
 define void @tail_indirect_call_void_void(void ()* %addr) {
 ; ALL-LABEL: tail_indirect_call_void_void:
 
 ; ALL:           move $25, $4
-; ALL:           jr $25
+; NOT-R6C:       jr   $[[TGT]]
+; R6C:           jrc  $[[TGT]]
 
   tail call void %addr()
   ret void
 }
 
 define i32 @tail_indirect_call_i32_void(i32 ()* %addr) {
 ; ALL-LABEL: tail_indirect_call_i32_void:
 
 ; ALL:           move $25, $4
-; ALL:           jr $25
+; NOT-R6C:       jr   $[[TGT]]
+; R6C:           jrc  $[[TGT]]
 
   %1 = tail call i32 %addr()
   ret i32 %1
 }
 
 define float @tail_indirect_call_float_void(float ()* %addr) {
 ; ALL-LABEL: tail_indirect_call_float_void:
 
 ; ALL:           move $25, $4
-; ALL:           jr $25
+; NOT-R6C:       jr   $[[TGT]]
+; R6C:           jrc  $[[TGT]]
 
   %1 = tail call float %addr()
   ret float %1
 }
 
 ; Check that passing undef as a double value doesn't cause machine code errors
 ; for FP64.
 declare hidden void @undef_double(i32 %this, double %volume) unnamed_addr align 2
 
 define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr align 2 {
 ; ALL-LABEL: thunk_undef_double:
 ; O32: # implicit-def: %A2
 ; O32: # implicit-def: %A3
-; ALL:        jr $25
+; NOT-R6C:    jr   $[[TGT]]
+; R6C:        jrc  $[[TGT]]
 
   tail call void @undef_double(i32 undef, double undef) #8
   ret void
 }
 
 ; Check that immediate addresses do not use jal.
 define i32 @jal_only_allows_symbols() {
 ; ALL-LABEL: jal_only_allows_symbols:

llvm/trunk/test/CodeGen/Mips/nacl-branch-delay.ll

 
 ; CHECK-NACL:             jr      $ra
 ; CHECK-NACL-NEXT:        nop
 }
 
 
 define void @test2() {
   store i32 1, i32* @x, align 4
-  tail call void @f2()
+  call void @f2()
   ret void
 
 
 ; CHECK-LABEL:       test2
 
 ; Check that branch-delay slot is used for storing to x before function call.
 
 ; CHECK:             jal

llvm/trunk/test/CodeGen/Mips/tailcall.ll

-; RUN: llc -march=mipsel -relocation-model=pic -enable-mips-tail-calls \
+; RUN: llc -march=mipsel -relocation-model=pic  \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s -check-prefix=PIC32
-; RUN: llc -march=mipsel -relocation-model=static -enable-mips-tail-calls \
+; RUN: llc -march=mipsel -relocation-model=static  \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s -check-prefix=STATIC32
-; RUN: llc -march=mips64el -mcpu=mips64r2 -enable-mips-tail-calls \
+; RUN: llc -march=mips64el -mcpu=mips64r2  \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s -check-prefix=N64
 ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic \
-; RUN:     -enable-mips-tail-calls -verify-machineinstrs < %s | \
+; RUN:      -verify-machineinstrs < %s | \
 ; RUN:     FileCheck %s -check-prefix=PIC16
 
+; RUN: llc -march=mipsel -relocation-model=pic -mattr=+micromips < %s | \
+; RUN:     FileCheck %s -check-prefix=PIC32
+; RUN: llc -march=mipsel -relocation-model=static -mattr=+micromips \
+; RUN:     < %s | FileCheck %s -check-prefix=STATIC32
+
+; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 < %s | \
+; RUN:     FileCheck %s -check-prefix=PIC32
+; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
+; RUN:     < %s | FileCheck %s -check-prefix=STATIC32
+; RUN: llc -march=mips64el -mcpu=mips64r6  \
+; RUN:     < %s | FileCheck %s -check-prefix=N64
+
+; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mattr=+micromips \
+; RUN:      < %s | FileCheck %s -check-prefix=PIC32
+; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
+; RUN:     -mattr=+micromips < %s | FileCheck %s -check-prefix=STATIC32
+; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+micromips < %s \
+; RUN:      | FileCheck %s -check-prefix=N64
+
 @g0 = common global i32 0, align 4
 @g1 = common global i32 0, align 4
 @g2 = common global i32 0, align 4
 @g3 = common global i32 0, align 4
 @g4 = common global i32 0, align 4
 @g5 = common global i32 0, align 4
 @g6 = common global i32 0, align 4
 @g7 = common global i32 0, align 4
; PIC16: jalrc
   ret i32 %call
 }
 
 declare i32 @callee4(i32, i32, i32, i32, i32, i32, i32, i32, i32)
 
 define i32 @caller5() nounwind readonly {
 entry:
 ; PIC32: .ent caller5
-; PIC32-NOT: jalr
+; PIC32-NOT: jalr $25
 ; PIC32: .end caller5
 ; STATIC32: .ent caller5
 ; STATIC32-NOT: jal
 ; STATIC32: .end caller5
 ; N64: .ent caller5
-; N64-NOT: jalr
+; N64-NOT: jalr $25
 ; N64: .end caller5
 ; PIC16: .ent caller5
 ; PIC16: jalrc
 ; PIC16: .end caller5
 
   %0 = load i32, i32* @g0, align 4
   %1 = load i32, i32* @g1, align 4
   %2 = load i32, i32* @g2, align 4
entry:
   %add8 = add nsw i32 %add7, %a9
   ret i32 %add8
 }
 
 declare i32 @callee8(i32, ...)
 
 define i32 @caller8_0() nounwind {
 entry:
+; PIC32: .ent caller8_0
+; PIC32: jr
+; PIC32: .end caller8_0
+; STATIC32: .ent caller8_0
+; STATIC32: j
+; STATIC32: .end caller8_0
+; N64: .ent caller8_0
+; N64-NOT: jalr $25
+; N64: .end caller8_0
+; PIC16: .ent caller8_0
+; PIC16: jalrc
+; PIC16: .end caller8_0
+
   %call = tail call fastcc i32 @caller8_1()
   ret i32 %call
 }
 
 define internal fastcc i32 @caller8_1() nounwind noinline {
 entry:
 ; PIC32: .ent caller8_1
 ; PIC32: jalr
 ; PIC32: .end caller8_1
 ; STATIC32: .ent caller8_1
 ; STATIC32: jal
 ; STATIC32: .end caller8_1
 ; N64: .ent caller8_1
-; N64-NOT: jalr
+; N64-NOT: jalr $25
 ; N64: .end caller8_1
 ; PIC16: .ent caller8_1
 ; PIC16: jalrc
 ; PIC16: .end caller8_1
 
   %call = tail call i32 (i32, ...) @callee8(i32 2, i32 1) nounwind
   ret i32 %call
 }
 
 %struct.S = type { [2 x i32] }
 
 @gs1 = external global %struct.S
 
 declare i32 @callee9(%struct.S* byval)
 
 define i32 @caller9_0() nounwind {
 entry:
+; PIC32: .ent caller9_0
+; PIC32: jr
+; PIC32: .end caller9_0
+; STATIC32: .ent caller9_0
+; STATIC32: j
+; STATIC32: .end caller9_0
+; N64: .ent caller9_0
+; N64-NOT: jalr $25
+; N64: .end caller9_0
+; PIC16: .ent caller9_0
+; PIC16: jalrc
+; PIC16: .end caller9_0
   %call = tail call fastcc i32 @caller9_1()
   ret i32 %call
 }
 
 define internal fastcc i32 @caller9_1() nounwind noinline {
 entry:
 ; PIC32: .ent caller9_1
 ; PIC32: jalr
; PIC16: .end caller9_1
   ret i32 %call
 }
 
 declare i32 @callee10(i32, i32, i32, i32, i32, i32, i32, i32, i32)
 
 define i32 @caller10(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8) nounwind {
 entry:
 ; PIC32: .ent caller10
-; PIC32-NOT: jalr
+; PIC32-NOT: jalr $25
 ; STATIC32: .ent caller10
 ; STATIC32-NOT: jal
 ; N64: .ent caller10
-; N64-NOT: jalr
+; N64-NOT: jalr $25
 ; PIC16: .ent caller10
 ; PIC16: jalrc
 
   %call = tail call i32 @callee10(i32 %a8, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind
   ret i32 %call
 }
 
 declare i32 @callee11(%struct.S* byval)

 
 define i32 @caller13() nounwind {
 entry:
 ; PIC32: .ent caller13
 ; PIC32-NOT: jalr
 ; STATIC32: .ent caller13
 ; STATIC32-NOT: jal
 ; N64: .ent caller13
-; N64-NOT: jalr
+; N64-NOT: jalr $25
 ; PIC16: .ent caller13
 ; PIC16: jalrc
 
   %call = tail call i32 (i32, ...) @callee13(i32 1, i32 2) nounwind
   ret i32 %call
 }
 
 ; Check that there is a chain edge between the load and store nodes.