[Sparc][LEON] Erratum fix. Insert NOP after LD or LDF instruction

[lero_chris]

Summary

Due to an erratum in some versions of LEON, we must insert a NOP after any LD or LDF instruction to ensure the processor has time to load the value correctly before using it. This pass will implement that erratum fix.

[jacob_hansen]

lib/Target/Sparc/LeonPasses.cpp

24

remove out-commented code.

34

please limit your lines to 80 columns, there's a few other instances of this.

52

Please remove these out-commented lines of code (or change to debug output), this and on line 60 and 71.

lib/Target/Sparc/SparcTargetMachine.h

39

It looks like you may have used an outdated trunk when generating this diff. SparcTargetMachine no longer have a Subtarget member, and the implementation of getSubtargetImpl have changed in the trunk compared to the code here.

[lero_chris]

• Changes to feature lists on processors to correct mistakes in which processors need errata fixes.
• Changes to getSubtargetImpl to be consistent with the implementation in, e.g. the ARM backend.

[lero_chris]

Micor formatting changes and removal of commented-out code.

[lero_chris]

Closed and committed after modifications applying to comments and no further activity.

lib/Target/Sparc/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS Sparc.td)
 
 tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM SparcGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM SparcGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM SparcGenSubtargetInfo.inc -gen-subtarget)
 tablegen(LLVM SparcGenCallingConv.inc -gen-callingconv)
 add_public_tablegen_target(SparcCommonTableGen)
 
 add_llvm_target(SparcCodeGen
   DelaySlotFiller.cpp
+  LeonPasses.cpp
   SparcAsmPrinter.cpp
   SparcInstrInfo.cpp
   SparcISelDAGToDAG.cpp
   SparcISelLowering.cpp
   SparcFrameLowering.cpp
   SparcMachineFunctionInfo.cpp
   SparcRegisterInfo.cpp
   SparcSubtarget.cpp

lib/Target/Sparc/LeonFeatures.td

 
 //support to casa instruction; for leon3 subtarget only
 def LeonCASA : SubtargetFeature<
   "hasleoncasa", 
   "HasLeonCasa", 
   "true", 
   "Enable CASA instruction for LEON3 and LEON4 processors"
 >;
+
+def InsertNOPLoad: SubtargetFeature<
+  "insertnopload",
+  "InsertNOPLoad",
+  "true",
+  "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction" 
+>;
 
 

lib/Target/Sparc/LeonPasses.h

+//===------- LeonPasses.h - Define passes specific to LEON ----------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_SPARC_LEON_PASSES_H
+#define LLVM_LIB_TARGET_SPARC_LEON_PASSES_H
+
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+
+#include "Sparc.h"
+#include "SparcSubtarget.h"
+
+using namespace llvm;
+
+class LEONMachineFunctionPass : public MachineFunctionPass {
+protected:
+  const SparcSubtarget *Subtarget;
+
+protected:
+  LEONMachineFunctionPass(TargetMachine &tm, char& ID);
+  LEONMachineFunctionPass(char& ID);
+};
+
+class InsertNOPLoad : public LEONMachineFunctionPass {
+public:
+  static char ID;
+
+  InsertNOPLoad(TargetMachine &tm);
+  bool runOnMachineFunction(MachineFunction& MF) override;
+
+  const char *getPassName() const override {
+    return "InsertNOPLoad: Erratum Fix LBR35: insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction";
+  }
+};
+
+#endif

lib/Target/Sparc/LeonPasses.cpp

+//===------ LeonPasses.cpp - Define passes specific to LEON ---------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "LeonPasses.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/ISDOpcodes.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/IR/LLVMContext.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+
+LEONMachineFunctionPass::LEONMachineFunctionPass(TargetMachine &tm, char& ID) :
+MachineFunctionPass(ID)/*,
+    TM(tm)*/
+{
+}
+
+LEONMachineFunctionPass::LEONMachineFunctionPass(char& ID) :
+                    MachineFunctionPass(ID)
+{
+}
+
+//****************************************************************************************************************
+//**** InsertNOPLoad pass
+//****************************************************************************************************************
+//This pass inserts a NOP after any LD or LDF instruction.
+//
+char InsertNOPLoad::ID = 0;
+
+InsertNOPLoad::InsertNOPLoad(TargetMachine &tm) :
+                    LEONMachineFunctionPass(tm, ID)
+{
+}
+
+bool InsertNOPLoad::runOnMachineFunction(MachineFunction& MF)
+{
+  Subtarget = &MF.getSubtarget<SparcSubtarget>();
+  const TargetInstrInfo& TII = *Subtarget->getInstrInfo();
+  DebugLoc DL = DebugLoc();
+
+  //errs() << "InsertNOPLoad on function " << MF.getName() << "\n";
+
+  bool Modified = false;
+  for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
+    MachineBasicBlock &MBB = *MFI;
+    for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++ MBBI) {
+      MachineInstr &MI = *MBBI;
+      unsigned Opcode = MI.getOpcode();
+      if (Opcode >=  SP::LDDArr && Opcode <= SP::LDrr) {
+        //errs() << "Inserting NOP after LD instruction\n";
+        MachineBasicBlock::iterator NMBBI = std::next(MBBI);
+        BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
+        Modified = true;
+      }
+      else if (MI.isInlineAsm()) {
+        std::string AsmString (MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName());
+        std::string LDOpCoode ("ld");
+        std::transform(AsmString.begin(), AsmString.end(), AsmString.begin(), ::tolower);
+        if (AsmString.find(LDOpCoode) == 0) // this is an inline ld/ldf instruction
+        {
+          //errs() << "Inserting NOP after LD instruction\n";
+          MachineBasicBlock::iterator NMBBI = std::next(MBBI);
+          BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
+          Modified = true;
+        }
+      }
+    }
+  }
+
+  return Modified;
+}

lib/Target/Sparc/Sparc.td

 
 // LEON 2 FT generic
 def : Processor<"leon2", LEON2Itineraries,
                 [FeatureLeon]>;
 
 // LEON 2 FT (AT697E)
 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
 def : Processor<"at697e", LEON2Itineraries,
-                [FeatureLeon]>;
+                [FeatureLeon, InsertNOPLoad]>;
 
 // LEON 2 FT (AT697F)
 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
 def : Processor<"at697f", LEON2Itineraries,
-                [FeatureLeon]>;
+                [FeatureLeon, InsertNOPLoad]>;
 
 
 // LEON 3 FT generic
 def : Processor<"leon3", LEON3Itineraries,
                 [FeatureLeon, UMACSMACSupport]>;
 
 // LEON 3 FT (UT699). Provides features for the UT699 processor
 // - covers all the erratum fixes for LEON3, but does not support the CASA instruction.
 def : Processor<"ut699", LEON3Itineraries, 
-                [FeatureLeon, UMACSMACSupport]>;
+                [FeatureLeon, InsertNOPLoad]>;
 
 // LEON3 FT (GR712RC). Provides features for the GR712RC processor.
 // - covers all the erratum fixed for LEON3 and support for the CASA instruction. 
 def : Processor<"gr712rc", LEON3Itineraries,
-                [FeatureLeon, UMACSMACSupport, LeonCASA]>;
+                [FeatureLeon, LeonCASA]>;
 
 // LEON 4 FT generic
 def : Processor<"leon4", LEON4Itineraries,
                 [FeatureLeon, UMACSMACSupport, LeonCASA]>;
 
 // LEON 4 FT (GR740) 
 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
 def : Processor<"gr740", LEON4Itineraries, 

lib/Target/Sparc/SparcISelLowering.h

public:
     ConstraintType getConstraintType(StringRef Constraint) const override;
     ConstraintWeight
     getSingleConstraintMatchWeight(AsmOperandInfo &info,
                                    const char *constraint) const override;
     void LowerAsmOperandForConstraint(SDValue Op,
                                       std::string &Constraint,
                                       std::vector<SDValue> &Ops,
                                       SelectionDAG &DAG) const override;
+
+    unsigned
+    getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+      if (ConstraintCode == "o")
+        return InlineAsm::Constraint_o;
+      return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
+    }
+
     std::pair<unsigned, const TargetRegisterClass *>
     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                  StringRef Constraint, MVT VT) const override;
 
     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
     MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
       return MVT::i32;
     }

lib/Target/Sparc/SparcISelLowering.cpp

SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
 
   // ATOMICs.
   // Atomics are supported on SparcV9. 32-bit atomics are also
   // supported by some Leon SparcV8 variants. Otherwise, atomics
   // are unsupported.
   if (Subtarget->isV9())
     setMaxAtomicSizeInBitsSupported(64);
   else if (false && Subtarget->hasLeonCasa())
     // Test made to fail pending completion of AtomicExpandPass,
     // as this will cause a regression until that work is completed.
     setMaxAtomicSizeInBitsSupported(32);
   else
     setMaxAtomicSizeInBitsSupported(0);
 
   setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal);
 
   setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
 

lib/Target/Sparc/SparcSubtarget.h

class SparcSubtarget : public SparcGenSubtargetInfo {
   bool Is64Bit;
   bool HasHardQuad;
   bool UsePopc;
   bool UseSoftFloat;
 
   // LEON features
   bool HasUmacSmac;
   bool HasLeonCasa;
+  bool InsertNOPLoad;
 
   SparcInstrInfo InstrInfo;
   SparcTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
   SparcFrameLowering FrameLowering;
 
 public:
   SparcSubtarget(const Triple &TT, const std::string &CPU,
public:
   bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
   bool hasHardQuad() const { return HasHardQuad; }
   bool usePopc() const { return UsePopc; }
   bool useSoftFloat() const { return UseSoftFloat; }
 
   // Leon options
   bool hasUmacSmac() const { return HasUmacSmac; }
   bool hasLeonCasa() const { return HasLeonCasa; }
+  bool insertNOPLoad() const { return InsertNOPLoad; }
 
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
   SparcSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
   bool is64Bit() const { return Is64Bit; }
 

lib/Target/Sparc/SparcSubtarget.cpp

SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
   IsVIS = false;
   HasHardQuad = false;
   UsePopc = false;
   UseSoftFloat = false;
 
   // Leon features
   HasLeonCasa = false;
   HasUmacSmac = false;
+  InsertNOPLoad = false;
 
   // Determine default and user specified characteristics
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = (Is64Bit) ? "v9" : "v8";
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, FS);

lib/Target/Sparc/SparcTargetMachine.h

 #include "SparcInstrInfo.h"
 #include "SparcSubtarget.h"
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
 
 class SparcTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
+  SparcSubtarget Subtarget;
   bool is64Bit;
   mutable StringMap<std::unique_ptr<SparcSubtarget>> SubtargetMap;
 public:
   SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
                      Optional<Reloc::Model> RM, CodeModel::Model CM,
                      CodeGenOpt::Level OL, bool is64bit);
   ~SparcTargetMachine() override;
 
+  const SparcSubtarget *getSubtargetImpl() const { return &Subtarget; }
   const SparcSubtarget *getSubtargetImpl(const Function &) const override;
 
   // Pass Pipeline Configuration
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
 };
 
 /// Sparc 32-bit target machine
 ///
 class SparcV8TargetMachine : public SparcTargetMachine {

lib/Target/Sparc/SparcTargetMachine.cpp

 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 //
 //===----------------------------------------------------------------------===//
 
 #include "SparcTargetMachine.h"
 #include "SparcTargetObjectFile.h"
 #include "Sparc.h"
+#include "LeonPasses.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/Support/TargetRegistry.h"
 using namespace llvm;
 
 extern "C" void LLVMInitializeSparcTarget() {
   // Register the target.

 SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Optional<Reloc::Model> RM,
                                        CodeModel::Model CM,
                                        CodeGenOpt::Level OL, bool is64bit)
     : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
                         getEffectiveRelocModel(RM), CM, OL),
-      TLOF(make_unique<SparcELFTargetObjectFile>()) {
+      TLOF(make_unique<SparcELFTargetObjectFile>()),
+      Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) {
   initAsmInfo();
-  this->is64Bit = is64bit;
 }
 
 SparcTargetMachine::~SparcTargetMachine() {}
 
 const SparcSubtarget * 
 SparcTargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");

 
 bool SparcPassConfig::addInstSelector() {
   addPass(createSparcISelDag(getSparcTargetMachine()));
   return false;
 }
 
 void SparcPassConfig::addPreEmitPass(){
   addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
+
+  if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad())
+  {
+    addPass(new InsertNOPLoad(getSparcTargetMachine()));
+  }
 }
 
 void SparcV8TargetMachine::anchor() { }
 
 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
                                            StringRef CPU, StringRef FS,
                                            const TargetOptions &Options,
                                            Optional<Reloc::Model> RM,

test/CodeGen/SPARC/LeonInsertNOPLoadPassUT.ll

+; RUN: llc %s -O0 -march=sparc -mcpu=ut699 -o - | FileCheck %s
+; RUN: llc %s -O0 -march=sparc -mcpu=leon3 -mattr=+insertnopload -o - | FileCheck %s
+
+; CHECK-LABEL: ld_float_test
+; CHECK:       ld [%o0+%lo(.LCPI0_0)], %f0
+; CHECK-NEXT:  nop
+define float @ld_float_test() #0 {
+entry:
+  %f = alloca float, align 4
+  store float 0x3FF3C08320000000, float* %f, align 4
+  %0 = load float, float* %f, align 4
+  ret float %0
+}
+
+; CHECK-LABEL: ld_i32_test
+; CHECK:       ld [%o0], %o0
+; CHECK-NEXT:  nop
+define i32 @ld_i32_test(i32 *%p) {
+  %res = load i32, i32* %p
+  ret i32 %res
+}
+
+; CHECK-LABEL: ld_inlineasm_test_1
+; CHECK:       ld [%o0], %o0
+; CHECK-NEXT:  !NO_APP
+; CHECK-NEXT:  nop
+define float @ld_inlineasm_test_1(float* %a) {
+entry:
+  %res = tail call float asm sideeffect "ld [$1], $0", "=r,r"(float* %a)
+
+  ret float %res
+}
+
+; CHECK-LABEL: ld_inlineasm_test_2
+; CHECK:       ld [%o0], %o0
+; CHECK-NEXT:  !NO_APP
+; CHECK-NEXT:  nop
+define i32 @ld_inlineasm_test_2(i32* %a) {
+entry:
+  %res = tail call i32 asm sideeffect "ld [$1], $0", "=r,r"(i32* %a)
+
+  ret i32 %res
+}
 No newline at end of file