Add support for Code16GCC

[niravd]

Summary

[X86] The Code16GCC directive parses X86 assembly input in 32-bit mode and
outputs in 16-bit mode. Teach Parser to switch modes appropriately.

[dwmw2]

Hm, why? We already added -m16 support to both GCC and Clang. So why would anyone use .code16gcc any more? It's just legacy.

And the *only* reason you'd use it is by putting asm(".code16gcc") at the start of a C file (which has problems with ensuring it's *first* in the asm output, which is why -m16 is so much better even in GCC). And didn't I see separately you forbade inline asm from leaving the assembler in a different mode to the one it starts in?

[niravd]

In D20109#425880, @dwmw2 wrote:

Hm, why? We already added -m16 support to both GCC and Clang. So why would anyone use .code16gcc any more? It's just legacy.

And the *only* reason you'd use it is by putting asm(".code16gcc") at the start of a C file (which has problems with ensuring it's *first* in the asm output, which is why -m16 is so much better even in GCC). And didn't I see separately you forbade inline asm from leaving the assembler in a different mode to the one it starts in?

Agreed. It's not particularlly worthwhile as one could rewrite the code. Further, that one use example (asm(".code16gcc")) doesn't do anything as we do not preserve modes changes from inline assembly (which is the only reasonable way to deal with it persistant inline asm changes) (see: http://reviews.llvm.org/D20067). The only thing this does is let the integrated assembler automatically do the rewriting.

[niravd]

Ping

[niravd]

Ping.

[jyknight]

In D20109#425880, @dwmw2 wrote:

Hm, why? We already added -m16 support to both GCC and Clang. So why would anyone use .code16gcc any more? It's just legacy.

People do seem to use it in asm files, presumably for the same reason GCC used it: you get the same behavior of the textual assembly targetting 16-bit processor mode, as you would if it were running in a 32-bit processor mode.

Since LLVM's assembler is not only intended for inline asm in C, but also as an actual assembler, I think it makes fine sense to support this directive.

[niravd]

rebase and do minor cosmetic cleanup

[niravd]

Ping.

[jyknight]

LGTM, modulo the one comment.

lib/Target/X86/AsmParser/X86AsmParser.cpp

64

Please put this variable with the other instance variables above.

lib/Target/X86/AsmParser/X86AsmParser.cpp

 };
 
 class X86AsmParser : public MCTargetAsmParser {
   const MCInstrInfo &MII;
   ParseInstructionInfo *InstInfo;
   std::unique_ptr<X86AsmInstrumentation> Instrumentation;
 
 private:
+  bool Code16GCC;
   SMLoc consumeToken() {
     MCAsmParser &Parser = getParser();
     SMLoc Result = Parser.getTok().getLoc();
     Parser.Lex();
     return Result;
   }
 
+  unsigned MatchInstruction(const OperandVector &Operands, MCInst &Inst,
+                            uint64_t &ErrorInfo, bool matchingInlineAsm,
+                            unsigned VariantID = 0) {
+    // In Code16GCC mode, match as 32-bit.
+    if (Code16GCC)
+      SwitchMode(X86::Mode32Bit);
+    unsigned rv = MatchInstructionImpl(Operands, Inst, ErrorInfo,
+                                       matchingInlineAsm, VariantID);
+    if (Code16GCC)
+      SwitchMode(X86::Mode16Bit);
+    return rv;
+  }
+
   enum InfixCalculatorTok {
     IC_OR = 0,
     IC_XOR,
     IC_AND,
     IC_LSHIFT,
     IC_RSHIFT,
     IC_PLUS,
     IC_MINUS,

 #define GET_ASSEMBLER_HEADER
 #include "X86GenAsmMatcher.inc"
 
   /// }
 
 public:
   X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
                const MCInstrInfo &mii, const MCTargetOptions &Options)
-    : MCTargetAsmParser(Options, sti), MII(mii), InstInfo(nullptr) {
+      : MCTargetAsmParser(Options, sti), MII(mii), InstInfo(nullptr),
+        Code16GCC(false) {
 
     // Initialize the set of available features.
     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
     Instrumentation.reset(
         CreateX86AsmInstrumentation(Options, Parser.getContext(), STI));
   }
 
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
bool X86AsmParser::ParseRegister(unsigned &RegNo,
   return false;
 }
 
 void X86AsmParser::SetFrameRegister(unsigned RegNo) {
   Instrumentation->SetInitialFrameRegister(RegNo);
 }
 
 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
-  unsigned basereg =
-    is64BitMode() ? X86::RSI : (is32BitMode() ? X86::ESI : X86::SI);
+  bool Parse32 = is32BitMode() || Code16GCC;
+  unsigned Basereg = is64BitMode() ? X86::RSI : (Parse32 ? X86::ESI : X86::SI);
   const MCExpr *Disp = MCConstantExpr::create(0, getContext());
   return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
-                               /*BaseReg=*/basereg, /*IndexReg=*/0, /*Scale=*/1,
+                               /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
                                Loc, Loc, 0);
 }
 
 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
-  unsigned basereg =
-    is64BitMode() ? X86::RDI : (is32BitMode() ? X86::EDI : X86::DI);
+  bool Parse32 = is32BitMode() || Code16GCC;
+  unsigned Basereg = is64BitMode() ? X86::RDI : (Parse32 ? X86::EDI : X86::DI);
   const MCExpr *Disp = MCConstantExpr::create(0, getContext());
   return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
-                               /*BaseReg=*/basereg, /*IndexReg=*/0, /*Scale=*/1,
+                               /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
                                Loc, Loc, 0);
 }
 
 bool X86AsmParser::IsSIReg(unsigned Reg) {
   switch (Reg) {
   default: llvm_unreachable("Only (R|E)SI and (R|E)DI are expected!");
   case X86::RSI:
   case X86::ESI:
if (ParseIntelIdentifier(Val, Identifier, Info,
     return nullptr;
 
   // Don't emit the offset operator.
   InstInfo->AsmRewrites->emplace_back(AOK_Skip, OffsetOfLoc, 7);
 
   // The offset operator will have an 'r' constraint, thus we need to create
   // register operand to ensure proper matching.  Just pick a GPR based on
   // the size of a pointer.
-  unsigned RegNo =
-      is64BitMode() ? X86::RBX : (is32BitMode() ? X86::EBX : X86::BX);
+  bool Parse32 = is32BitMode() || Code16GCC;
+  unsigned RegNo = is64BitMode() ? X86::RBX : (Parse32 ? X86::EBX : X86::BX);
+
   return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
                                OffsetOfLoc, Identifier, Info.OpDecl);
 }
 
 enum IntelOperatorKind {
   IOK_LENGTH,
   IOK_SIZE,
   IOK_TYPE
bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
 
   // First, handle aliases that expand to multiple instructions.
   MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
 
   bool WasOriginallyInvalidOperand = false;
   MCInst Inst;
 
   // First, try a direct match.
-  switch (MatchInstructionImpl(Operands, Inst,
-                               ErrorInfo, MatchingInlineAsm,
-                               isParsingIntelSyntax())) {
+  switch (MatchInstruction(Operands, Inst, ErrorInfo, MatchingInlineAsm,
   default: llvm_unreachable("Unexpected match result!");
   case Match_Success:
     // Some instructions need post-processing to, for example, tweak which
     // encoding is selected. Loop on it while changes happen so the
     // individual transformations can chain off each other.
     if (!MatchingInlineAsm)
       while (processInstruction(Inst, Operands))
         ;
bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
 
   // Check for the various suffix matches.
   uint64_t ErrorInfoIgnore;
   uint64_t ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings.
   unsigned Match[4];
 
   for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) {
     Tmp.back() = Suffixes[I];
-    Match[I] = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
-                                  MatchingInlineAsm, isParsingIntelSyntax());
+    Match[I] = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
     // If this returned as a missing feature failure, remember that.
     if (Match[I] == Match_MissingFeature)
       ErrorInfoMissingFeature = ErrorInfoIgnore;
   }
 
   // Restore the old token.
   Op.setTokenValue(Base);
 
bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
   SmallVector<unsigned, 8> Match;
   uint64_t ErrorInfoMissingFeature = 0;
   if (UnsizedMemOp && UnsizedMemOp->isMemUnsized()) {
     static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512};
     for (unsigned Size : MopSizes) {
       UnsizedMemOp->Mem.Size = Size;
       uint64_t ErrorInfoIgnore;
       unsigned LastOpcode = Inst.getOpcode();
-      unsigned M =
-          MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
+      unsigned M = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
                                     MatchingInlineAsm, isParsingIntelSyntax());
       if (Match.empty() || LastOpcode != Inst.getOpcode())
         Match.push_back(M);
 
       // If this returned as a missing feature failure, remember that.
       if (Match.back() == Match_MissingFeature)
         ErrorInfoMissingFeature = ErrorInfoIgnore;
     }
 
     // Restore the size of the unsized memory operand if we modified it.
     if (UnsizedMemOp)
       UnsizedMemOp->Mem.Size = 0;
   }
 
   // If we haven't matched anything yet, this is not a basic integer or FPU
   // operation.  There shouldn't be any ambiguity in our mnemonic table, so try
   // matching with the unsized operand.
   if (Match.empty()) {
-    Match.push_back(MatchInstructionImpl(Operands, Inst, ErrorInfo,
-                                         MatchingInlineAsm,
-                                         isParsingIntelSyntax()));
+    Match.push_back(MatchInstruction(
+        Operands, Inst, ErrorInfo, MatchingInlineAsm, isParsingIntelSyntax()));
     // If this returned as a missing feature failure, remember that.
     if (Match.back() == Match_MissingFeature)
       ErrorInfoMissingFeature = ErrorInfo;
   }
 
   // Restore the size of the unsized memory operand if we modified it.
   if (UnsizedMemOp)
     UnsizedMemOp->Mem.Size = 0;
bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
   Parser.Lex();
   return false;
 }
 
 /// ParseDirectiveCode
 ///  ::= .code16 | .code32 | .code64
 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
   MCAsmParser &Parser = getParser();
+  Code16GCC = false;
   if (IDVal == ".code16") {
     Parser.Lex();
     if (!is16BitMode()) {
       SwitchMode(X86::Mode16Bit);
       getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
     }
+  } else if (IDVal == ".code16gcc") {
+    // .code16gcc parses as if in 32-bit mode, but emits code in 16-bit mode.
+    Parser.Lex();
+    Code16GCC = true;
+    if (!is16BitMode()) {
+      SwitchMode(X86::Mode16Bit);
+      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
+    }
   } else if (IDVal == ".code32") {
     Parser.Lex();
     if (!is32BitMode()) {
       SwitchMode(X86::Mode32Bit);
       getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
     }
   } else if (IDVal == ".code64") {
     Parser.Lex();

test/MC/X86/code16gcc.s

+// RUN: llvm-mc -triple i386-unknown-unknown-unknown --show-encoding %s | FileCheck %s 
+
+  .code16gcc
+  //CHECK:  .code16
+  nop
+  //CHECK:  nop                             # encoding: [0x90]
+  lodsb
+  //CHECK:  lodsb (%esi), %al             # encoding: [0x67,0xac]
+  lodsb (%si), %al
+  //CHECK:  lodsb (%si), %al              # encoding: [0xac]
+  lodsb (%esi), %al
+  //CHECK:  lodsb (%esi), %al             # encoding: [0x67,0xac]
+  lodsl %gs:(%esi)
+  //CHECK:  lodsl %gs:(%esi), %eax        # encoding: [0x66,0x65,0x67,0xad]
+  lods (%esi), %ax
+  //CHECK:  lodsw (%esi), %ax             # encoding: [0x67,0xad]
+  stosw
+  //CHECK:  stosw %ax, %es:(%edi)         # encoding: [0x67,0xab]
+  stos %eax, (%edi)
+  //CHECK:  stosl %eax, %es:(%edi)        # encoding: [0x66,0x67,0xab]
+  stosb %al, %es:(%edi)
+  //CHECK:  stosb %al, %es:(%edi)         # encoding: [0x67,0xaa]
+  scas %es:(%edi), %al
+  //CHECK:  scasb %es:(%edi), %al         # encoding: [0x67,0xae]
+  scas %es:(%di), %ax
+  //CHECK:  scasw %es:(%di), %ax          # encoding: [0xaf]
+  cmpsb
+  //CHECK:  cmpsb %es:(%edi), (%esi)      # encoding: [0x67,0xa6]
+  cmpsw (%edi), (%esi)
+  //CHECK:  cmpsw %es:(%edi), (%esi)      # encoding: [0x67,0xa7]
+  cmpsl %es:(%edi), %ss:(%esi)
+  //CHECK:  cmpsl %es:(%edi), %ss:(%esi)  # encoding: [0x66,0x36,0x67,0xa7]
+  movsb (%esi), (%edi)
+  //CHECK:  movsb (%esi), %es:(%edi)      # encoding: [0x67,0xa4]
+  movsl %gs:(%esi), (%edi)
+  //CHECK:  movsl %gs:(%esi), %es:(%edi)  # encoding: [0x66,0x65,0x67,0xa5]
+  outsb
+  //CHECK:  outsb (%esi), %dx             # encoding: [0x67,0x6e]
+  outsw %fs:(%esi), %dx
+  //CHECK:  outsw %fs:(%esi), %dx         # encoding: [0x64,0x67,0x6f]
+  insw %dx, (%di)
+  //CHECK:  insw  %dx, %es:(%di)          # encoding: [0x6d]
+  call $0x7ace,$0x7ace
+  //CHECK:  lcalll  $31438, $31438          # encoding: [0x66,0x9a,0xce,0x7a,0x00,0x00,0xce,0x7a]
+  ret
+  //CHECK:  retl                            # encoding: [0x66,0xc3]
+  pop %ss
+  //CHECK:  popl  %ss                     # encoding: [0x66,0x17]
+  enter $0x7ace,$0x7f
+  //CHECK:  enter $31438, $127            # encoding: [0xc8,0xce,0x7a,0x7f]
+  leave
+  //CHECK:  leave                           # encoding: [0xc9]
+  push %ss
+  //CHECK:  pushl %ss                     # encoding: [0x66,0x16]
+  pop %ss
+  //CHECK:  popl  %ss                     # encoding: [0x66,0x17]
+  popa
+  //CHECK:  popal                           # encoding: [0x66,0x61]
+  pushf
+  //CHECK:  pushfl                          # encoding: [0x66,0x9c]
+  popf
+  //CHECK:  popfl                           # encoding: [0x66,0x9d]
+  pushw 4
+  //CHECK:  pushw 4                       # encoding: [0xff,0x36,0x04,0x00]
+
+  
+