[AMDGPU] Move reserved vgpr count for trap handler usage to SIMachineFunctionInfo + minor commenting changes

[• tstellarAMD]

LGTM

lib/Target/AMDGPU/AMDGPUAsmPrinter.h

     uint32_t LDSSize;
     bool FlatUsed;
 
+    // If ReservedVGPRCount is 0 then must be 0. Otherwise, this is the first
+    // fixed VGPR number reserved.
     uint16_t ReservedVGPRFirst;
+    // The number of consecutive VGPRs reserved.
     uint16_t ReservedVGPRCount;
 
     // Bonus information for debugging.

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

   MaxSGPR += ExtraSGPRs;
 
   // Update necessary Reserved* fields and max VGPRs used if
-  // "amdgpu-debugger-reserved-trap-regs" was specified.
+  // "amdgpu-debugger-reserve-trap-regs" attribute was specified.
   if (STM.debuggerReserveTrapVGPRs()) {
     ProgInfo.ReservedVGPRFirst = MaxVGPR + 1;
-    ProgInfo.ReservedVGPRCount = STM.debuggerReserveTrapVGPRCount();
-    MaxVGPR += STM.debuggerReserveTrapVGPRCount();
+    ProgInfo.ReservedVGPRCount = MFI->getDebuggerReserveTrapVGPRCount();
+    MaxVGPR += MFI->getDebuggerReserveTrapVGPRCount();
   }
 
   // We found the maximum register index. They start at 0, so add one to get the

lib/Target/AMDGPU/AMDGPUSubtarget.h

     return DebuggerReserveTrapVGPRs;
   }
 
-  unsigned debuggerReserveTrapVGPRCount() const {
-    return debuggerReserveTrapVGPRs() ? 4 : 0;
-  }
-
   bool dumpCode() const {
     return DumpCode;
   }

lib/Target/AMDGPU/SIMachineFunctionInfo.h

 
   unsigned MaximumWorkGroupSize;
 
+  // Number of reserved VGPRs for trap handler usage.
+  unsigned DebuggerReserveTrapVGPRCount;
+
 public:
   // FIXME: Make private
   unsigned LDSWaveSpillSize;

     ReturnsVoid = Value;
   }
 
+  unsigned getDebuggerReserveTrapVGPRCount() const {
+    return DebuggerReserveTrapVGPRCount;
+  }
+
   unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const;
 };
 

lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

     PSInputAddr(0),
     ReturnsVoid(true),
     MaximumWorkGroupSize(0),
+    DebuggerReserveTrapVGPRCount(0),
     LDSWaveSpillSize(0),
     PSInputEna(0),
     NumUserSGPRs(0),

     MaximumWorkGroupSize = AMDGPU::getMaximumWorkGroupSize(*F);
   else
     MaximumWorkGroupSize = ST.getWavefrontSize();
+
+  if (ST.debuggerReserveTrapVGPRs())
+    DebuggerReserveTrapVGPRCount = 4;
 }
 
 unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(

lib/Target/AMDGPU/SIRegisterInfo.cpp

   // attribute was specified.
   const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
   if (ST.debuggerReserveTrapVGPRs()) {
-    for (unsigned i = MaxWorkGroupVGPRCount - ST.debuggerReserveTrapVGPRCount();
-           i < MaxWorkGroupVGPRCount; ++i) {
+    unsigned ReservedVGPRFirst =
+      MaxWorkGroupVGPRCount - MFI->getDebuggerReserveTrapVGPRCount();
+    for (unsigned i = ReservedVGPRFirst; i < MaxWorkGroupVGPRCount; ++i) {
       unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
       reserveRegisterTuples(Reserved, Reg);
     }