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Differential D19505

AMDGPU: Implement getLoadStoreVecRegBitWidth
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Authored by arsenm on Apr 25 2016, 3:13 PM.

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escha
arsenm
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arsenm updated this revision to Diff 54925.Apr 25 2016, 3:13 PM

arsenm retitled this revision from to AMDGPU: Implement getLoadStoreVecRegBitWidth.

arsenm updated this object.

arsenm added reviewers: escha, resistor, • tstellarAMD.

arsenm added a subscriber: llvm-commits.

Herald added a subscriber: arsenm. · View Herald TranscriptApr 25 2016, 3:13 PM

ping

r274312

This revision is now accepted and ready to land.Jun 30 2016, 6:03 PM

arsenm closed this revision.Jun 30 2016, 6:04 PM

Revision Contents

Path

Size

lib/

Target/

AMDGPU/

AMDGPUTargetTransformInfo.h

1 line

AMDGPUTargetTransformInfo.cpp

22 lines

Diff 54925

lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines	public:

TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) {		TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) {
assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");		assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
return ST->hasBCNT(TyWidth) ? TTI::PSK_FastHardware : TTI::PSK_Software;		return ST->hasBCNT(TyWidth) ? TTI::PSK_FastHardware : TTI::PSK_Software;
}		}

unsigned getNumberOfRegisters(bool Vector);		unsigned getNumberOfRegisters(bool Vector);
unsigned getRegisterBitWidth(bool Vector);		unsigned getRegisterBitWidth(bool Vector);
		unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace);
unsigned getMaxInterleaveFactor(unsigned VF);		unsigned getMaxInterleaveFactor(unsigned VF);

int getArithmeticInstrCost(		int getArithmeticInstrCost(
unsigned Opcode, Type *Ty,		unsigned Opcode, Type *Ty,
TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,		TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,		TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,		TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);		TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
Show All 10 Lines

lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines	unsigned AMDGPUTTIImpl::getNumberOfRegisters(bool Vec) {

return 4 * 128; // XXX - 4 channels. Should these count as vector instead?		return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
}		}

unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool Vector) {		unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool Vector) {
return Vector ? 0 : 32;		return Vector ? 0 : 32;
}		}

		unsigned AMDGPUTTIImpl::getLoadStoreVecRegBitWidth(unsigned AddrSpace) {
		switch (AddrSpace) {
		case AMDGPUAS::GLOBAL_ADDRESS:
		case AMDGPUAS::CONSTANT_ADDRESS:
		case AMDGPUAS::FLAT_ADDRESS:
		return 128;
		case AMDGPUAS::LOCAL_ADDRESS:
		case AMDGPUAS::REGION_ADDRESS:
		return 64;
		case AMDGPUAS::PRIVATE_ADDRESS:
		return 8 * ST->getMaxPrivateElementSize();
		default:
		if (ST->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS &&
		(AddrSpace == AMDGPUAS::PARAM_D_ADDRESS \|\|
		AddrSpace == AMDGPUAS::PARAM_I_ADDRESS \|\|
		(AddrSpace >= AMDGPUAS::CONSTANT_BUFFER_0 &&
		AddrSpace <= AMDGPUAS::CONSTANT_BUFFER_15)))
		return 128;
		llvm_unreachable("unhandled address space");
		}
		}

unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) {		unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) {
// Semi-arbitrary large amount.		// Semi-arbitrary large amount.
return 64;		return 64;
}		}

int AMDGPUTTIImpl::getArithmeticInstrCost(		int AMDGPUTTIImpl::getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,		unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,		TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
▲ Show 20 Lines • Show All 227 Lines • Show Last 20 Lines