Remove MinLatency in SchedMachineModel. NFC.

[flyingforyou]

Summary

We don't use MinLatency any more since r184032.

[atrick]

Thanks.

[flyingforyou]

Thanks @atrick.

Commited in r267502.

llvm/trunk/include/llvm/Target/TargetSchedule.td

 // is not overriden by the target.
 //
 // Target hooks allow subtargets to associate LoadLatency and
 // HighLatency with groups of opcodes.
 //
 // See MCSchedule.h for detailed comments.
 class SchedMachineModel {
   int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle.
-  int MinLatency = -1; // Determines which instructions are allowed in a group.
-                       // (-1) inorder (0) ooo, (1): inorder +var latencies.
   int MicroOpBufferSize = -1; // Max micro-ops that can be buffered.
   int LoopMicroOpBufferSize = -1; // Max micro-ops that can be buffered for
                                   // optimized loop dispatch/execution.
   int LoadLatency = -1; // Cycles for loads to access the cache.
   int HighLatency = -1; // Approximation of cycles for "high latency" ops.
   int MispredictPenalty = -1; // Extra cycles for a mispredicted branch.
 
   // Per-cycle resources tables.

llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td

 // ===---------------------------------------------------------------------===//
 // The following definitions describe the simpler per-operand machine model.
 // This works with MachineScheduler. See MCSchedModel.h for details.
 
 // Cortex-A53 machine model for scheduling and other instruction cost heuristics.
 def CortexA53Model : SchedMachineModel {
   let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
   let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
-  let MinLatency = 1 ;       // OperandCycles are interpreted as MinLatency.
   let LoadLatency = 3;       // Optimistic load latency assuming bypass.
                              // This is overriden by OperandCycles if the
                              // Itineraries are queried instead.
   let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
                              // Specification - Instruction Timings"
                              // v 1.0 Spreadsheet
   let CompleteModel = 1;
 }

llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td

 
 //===----------------------------------------------------------------------===//
 // The Exynos-M1 is a traditional superscalar microprocessor with a
 // 4-wide in-order stage for decode and dispatch and a wider issue stage.
 // The execution units and loads and stores are out-of-order.
 
 def ExynosM1Model : SchedMachineModel {
   let IssueWidth            =  4; // Up to 4 uops per cycle.
-  let MinLatency            =  0; // OoO.
   let MicroOpBufferSize     = 96; // ROB size.
   let LoopMicroOpBufferSize = 32; // Instruction queue size.
   let LoadLatency           =  4; // Optimistic load cases.
   let MispredictPenalty     = 14; // Minimum branch misprediction penalty.
   let CompleteModel         =  0; // Use the default model otherwise.
 }
 
 //===----------------------------------------------------------------------===//

llvm/trunk/lib/Target/ARM/ARMScheduleA8.td

 
 // ===---------------------------------------------------------------------===//
 // This following definitions describe the simple machine model which
 // will replace itineraries.
 
 // Cortex-A8 machine model for scheduling and other instruction cost heuristics.
 def CortexA8Model : SchedMachineModel {
   let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
-  let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
   let LoadLatency = 2; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
   let MispredictPenalty = 13; // Based on estimate of pipeline depth.
   let CompleteModel = 0;
 
   let Itineraries = CortexA8Itineraries;
 }

llvm/trunk/lib/Target/Lanai/LanaiSchedule.td

def LanaiSchedModel : SchedMachineModel {
 
   // Allow scheduler to assign default model to any unrecognized opcodes.
   // [default = 1]
   let CompleteModel = 0;
 
   // Max micro-ops that may be scheduled per cycle. [default = 1]
   let IssueWidth = 1;
 
-  // Determines which instructions are allowed in a group. 1 is an inorder
-  // CPU with variable latencies. [default = -1]
-  let MinLatency = 1;
-
   // Extra cycles for a mispredicted branch. [default = -1]
   let MispredictPenalty = 10;
 
   // Enable Post RegAlloc Scheduler pass. [default = 0]
   let PostRAScheduler = 0;
 
   // Max micro-ops that can be buffered. [default = -1]
   let MicroOpBufferSize = 0;

llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td

InstrItinData<IIC_FPRes,      [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                 [P440_FPR_Bypass, P440_FPR_Bypass]>
 ]>;
 
 // ===---------------------------------------------------------------------===//
 // PPC440 machine model for scheduling and other instruction cost heuristics.
 
 def PPC440Model : SchedMachineModel {
   let IssueWidth = 2;  // 2 instructions are dispatched per cycle.
-  let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
   let LoadLatency = 5; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
 
   let CompleteModel = 0;
 
   let Itineraries = PPC440Itineraries;
 }
 

llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td

InstrItinData<IIC_FPRes,       [InstrStage<1, [A2_FU]>],
                                  [6, 0]>
 ]>;
 
 // ===---------------------------------------------------------------------===//
 // A2 machine model for scheduling and other instruction cost heuristics.
 
 def PPCA2Model : SchedMachineModel {
   let IssueWidth = 1;  // 1 instruction is dispatched per cycle.
-  let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
   let LoadLatency = 6; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
   let MispredictPenalty = 13;
 
   let CompleteModel = 0;
 
   let Itineraries = PPCA2Itineraries;
 }
 

llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td

InstrItinData<IIC_FPRes,       [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
                                  [E500_FPR_Bypass, E500_FPR_Bypass]>
 ]>;
 
 // ===---------------------------------------------------------------------===//
 // e500mc machine model for scheduling and other instruction cost heuristics.
 
 def PPCE500mcModel : SchedMachineModel {
   let IssueWidth = 2;  // 2 micro-ops are dispatched per cycle.
-  let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
   let LoadLatency = 5; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
 
   let CompleteModel = 0;
 
   let Itineraries = PPCE500mcItineraries;
 }

llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td

InstrItinData<IIC_FPRes,       [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
                                  [E5500_FPR_Bypass, E5500_FPR_Bypass]>
 ]>;
 
 // ===---------------------------------------------------------------------===//
 // e5500 machine model for scheduling and other instruction cost heuristics.
 
 def PPCE5500Model : SchedMachineModel {
   let IssueWidth = 2;  // 2 micro-ops are dispatched per cycle.
-  let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
   let LoadLatency = 6; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
 
   let CompleteModel = 0;
 
   let Itineraries = PPCE5500Itineraries;
 }

llvm/trunk/lib/Target/PowerPC/PPCScheduleG5.td

def G5Itineraries : ProcessorItineraries<
   InstrItinData<IIC_VecVSR      , [InstrStage<3, [G5_VPU]>]>
 ]>;
 
 // ===---------------------------------------------------------------------===//
 // G5 machine model for scheduling and other instruction cost heuristics.
 
 def G5Model : SchedMachineModel {
   let IssueWidth = 4;  // 4 (non-branch) instructions are dispatched per cycle.
-  let MinLatency = 0;  // Out-of-order dispatch.
   let LoadLatency = 3; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
   let MispredictPenalty = 16;
 
   let CompleteModel = 0;
 
   let Itineraries = G5Itineraries;
 }
 

llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td

 // P7 machine model for scheduling and other instruction cost heuristics.
 
 def P7Model : SchedMachineModel {
   let IssueWidth = 6;  // 4 (non-branch) instructions are dispatched per cycle.
                        // Note that the dispatch bundle size is 6 (including
                        // branches), but the total internal issue bandwidth per
                        // cycle (from all queues) is 8.
 
-  let MinLatency = 0;  // Out-of-order dispatch.
   let LoadLatency = 3; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
   let MispredictPenalty = 16;
 
   // Try to make sure we have at least 10 dispatch groups in a loop.
   let LoopMicroOpBufferSize = 40;
 
   let CompleteModel = 0;
 
   let Itineraries = P7Itineraries;
 }
 

llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td

 // P8 has an 8 insn dispatch group (6 non-branch, 2 branch) and can issue up
 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
 
 def P8Model : SchedMachineModel {
   let IssueWidth = 8;  // up to 8 instructions dispatched per cycle.
                        // up to six non-branch instructions.
                        // up to two branches in a dispatch group.
 
-  let MinLatency = 0;  // Out-of-order dispatch.
   let LoadLatency = 3; // Optimistic load latency assuming bypass.
                        // This is overriden by OperandCycles if the
                        // Itineraries are queried instead.
   let MispredictPenalty = 16;
 
   // Try to make sure we have at least 10 dispatch groups in a loop.
   let LoopMicroOpBufferSize = 60;
 
   let CompleteModel = 0;
 
   let Itineraries = P8Itineraries;
 }