Add optimization bisect opt-in calls for AMDGPU passes

[andrew.w.kaylor]

Summary

This patch adds calls to AMDGPU-specific passes that can be safely skipped to opt-in to the optimization bisect mechanism.

The following passes are not calling the opt-in function:

AMDGPUAlwaysInline
AMDGPUAnnotateKernelFeatures
AMDGPUCFGStructurizer
AMDGPUOpenCLImageTypeLoweringPass
R600ControlFlowFinalizer
R600EmitClauseMarkers
R600ExpandSpecialInstrsPass
R600Packetizer
R600TextureIntrinsicsReplacer
SIAnnotateControlFlow
SIFixControlFlowLiveIntervals
SIFixSGPRCopies
SIInsertNops
SIInsertWaits
SILowerControlFlow
SILowerI1Copies
SITypeRewriter
SIWholeQuadMode

Note that the call to skipFunction() will also check for the "optnone" function attribute, so this can theoretically result in passes being skipped even when optimization bisect is not being done. However, I believe that any pass that can be safely skipped should be skipped for functions with the optnone attribute. Where the OptNone function attribute was being checked, it is now being checked within the call to skipFunction().

[arsenm]

LGTM

[probinson]

Note that the call to skipFunction() will also check for the "optnone" function attribute, so this can theoretically result in passes being skipped even when optimization bisect is not being done. However, I believe that any pass that can be safely skipped should be skipped for functions with the optnone attribute. Where the OptNone function attribute was being checked, it is now being checked within the call to skipFunction().

The original optnone implementation never got to targets other than X86, so thank you for this!

llvm/trunk/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp

 
 }
 
 bool AMDGPUAnnotateUniformValues::doInitialization(Module &M) {
   return false;
 }
 
 bool AMDGPUAnnotateUniformValues::runOnFunction(Function &F) {
+  if (skipFunction(F))
+    return false;
+
   DA = &getAnalysis<DivergenceAnalysis>();
   visit(F);
 
   return true;
 }
 
 FunctionPass *
 llvm::createAMDGPUAnnotateUniformValues() {
   return new AMDGPUAnnotateUniformValues();
 }

llvm/trunk/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp

bool AMDGPUPromoteAlloca::doInitialization(Module &M) {
 
   IsAMDGCN = TT.getArch() == Triple::amdgcn;
   IsAMDHSA = TT.getOS() == Triple::AMDHSA;
 
   return false;
 }
 
 bool AMDGPUPromoteAlloca::runOnFunction(Function &F) {
-  if (!TM || F.hasFnAttribute(Attribute::OptimizeNone))
+  if (!TM || skipFunction(F))
     return false;
 
   FunctionType *FTy = F.getFunctionType();
 
   // If the function has any arguments in the local address space, then it's
   // possible these arguments require the entire local memory space, so
   // we cannot use local memory in the pass.
   for (Type *ParamTy : FTy->params()) {

llvm/trunk/lib/Target/AMDGPU/R600ClauseMergePass.cpp

RootCFAlu->getOperand(KBank1LineIdx).setImm(
         LatrCFAlu->getOperand(KBank1LineIdx).getImm());
   }
   RootCFAlu->getOperand(CntIdx).setImm(CumuledInsts);
   RootCFAlu->setDesc(TII->get(LatrCFAlu->getOpcode()));
   return true;
 }
 
 bool R600ClauseMergePass::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(*MF.getFunction()))
+    return false;
+
   TII = static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo());
   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
                                                   BB != BB_E; ++BB) {
     MachineBasicBlock &MBB = *BB;
     MachineBasicBlock::iterator I = MBB.begin(),  E = MBB.end();
     MachineBasicBlock::iterator LatestCFAlu = E;
     while (I != E) {
       MachineInstr *MI = I++;

llvm/trunk/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp

void R600VectorRegMerger::trackRSI(const RegSeqInfo &RSI) {
   It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) {
     PreviousRegSeqByReg[(*It).first].push_back(RSI.Instr);
   }
   PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr);
   PreviousRegSeq[RSI.Instr] = RSI;
 }
 
 bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
+  if (skipFunction(*Fn.getFunction()))
+    return false;
+
   TII = static_cast<const R600InstrInfo *>(Fn.getSubtarget().getInstrInfo());
   MRI = &(Fn.getRegInfo());
   for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
        MBB != MBBe; ++MBB) {
     MachineBasicBlock *MB = &*MBB;
     PreviousRegSeq.clear();
     PreviousRegSeqByReg.clear();
     PreviousRegSeqByUndefCount.clear();

llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp

static void foldOperand(MachineOperand &OpToFold, MachineInstr *UseMI,
 
   // FIXME: We could try to change the instruction from 64-bit to 32-bit
   // to enable more folding opportunites.  The shrink operands pass
   // already does this.
   return;
 }
 
 bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(*MF.getFunction()))
+    return false;
+
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const SIInstrInfo *TII =
       static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
   const SIRegisterInfo &TRI = TII->getRegisterInfo();
 
   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
                                                   BI != BE; ++BI) {
 

llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
 
     ++I;
   }
 
   return Modified;
 }
 
 bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(*MF.getFunction()))
+    return false;
+
   const TargetSubtargetInfo &STM = MF.getSubtarget();
   TRI = static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
   TII = static_cast<const SIInstrInfo *>(STM.getInstrInfo());
   MRI = &MF.getRegInfo();
 
   LIS = &getAnalysis<LiveIntervals>();
 
   DEBUG(dbgs() << "Running SILoadStoreOptimizer\n");

llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp

return MachineOperand::CreateReg(Orig.getReg(),
                                    Orig.isInternalRead());
 }
 
 static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) {
   return isInt<16>(Src.getImm()) && !TII->isInlineConstant(Src, 4);
 }
 
 bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(*MF.getFunction()))
+    return false;
+
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const SIInstrInfo *TII =
       static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
   const SIRegisterInfo &TRI = TII->getRegisterInfo();
   std::vector<unsigned> I1Defs;
 
   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
                                                   BI != BE; ++BI) {