AMDGPU/SI: Fix regression with no-return atomics

[nhaehnle]

Summary

In the added test-case, the atomic instruction feeds into a non-machine
CopyToReg node which hasn't been selected yet, so guard against
non-machine opcodes here.

[arsenm]

LGTM

lib/Target/AMDGPU/SIISelLowering.cpp

if (NoRetAtomicOp != -1) {
 
     // For mubuf_atomic_cmpswap, we need to have tablegen use an extract_subreg
     // instruction, because the return type of these instructions is a vec2 of
     // the memory type, so it can be tied to the input operand.
     // This means these instructions always have a use, so we need to add a
     // special case to check if the atomic has only one extract_subreg use,
     // which itself has no uses.
     if ((Node->hasNUsesOfValue(1, 0) &&
+         Node->use_begin()->isMachineOpcode() &&
          Node->use_begin()->getMachineOpcode() == AMDGPU::EXTRACT_SUBREG &&
          !Node->use_begin()->hasAnyUseOfValue(0))) {
       unsigned Def = MI->getOperand(0).getReg();
 
       // Change this into a noret atomic.
       MI->setDesc(TII->get(NoRetAtomicOp));
       MI->RemoveOperand(0);
 

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll

 ; Since there probably isn't a reasonable use-case of cmpswap that discards
 ; the return value, that seems okay.
 ;
 ;  %unused = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o6, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
   %out = bitcast i32 %o6 to float
   ret float %out
 }
 
+;CHECK-LABEL: {{^}}test4:
+;CHECK: buffer_atomic_add v0,
+define amdgpu_ps float @test4() {
+main_body:
+  %v = call i32 @llvm.amdgcn.buffer.atomic.add(i32 1, <4 x i32> undef, i32 0, i32 4, i1 false)
+  %v.float = bitcast i32 %v to float
+  ret float %v.float
+}
+
 declare i32 @llvm.amdgcn.buffer.atomic.swap(i32, <4 x i32>, i32, i32, i1) #0
 declare i32 @llvm.amdgcn.buffer.atomic.add(i32, <4 x i32>, i32, i32, i1) #0
 declare i32 @llvm.amdgcn.buffer.atomic.sub(i32, <4 x i32>, i32, i32, i1) #0
 declare i32 @llvm.amdgcn.buffer.atomic.smin(i32, <4 x i32>, i32, i32, i1) #0
 declare i32 @llvm.amdgcn.buffer.atomic.umin(i32, <4 x i32>, i32, i32, i1) #0
 declare i32 @llvm.amdgcn.buffer.atomic.smax(i32, <4 x i32>, i32, i32, i1) #0
 declare i32 @llvm.amdgcn.buffer.atomic.umax(i32, <4 x i32>, i32, i32, i1) #0
 declare i32 @llvm.amdgcn.buffer.atomic.and(i32, <4 x i32>, i32, i32, i1) #0
 declare i32 @llvm.amdgcn.buffer.atomic.or(i32, <4 x i32>, i32, i32, i1) #0
 declare i32 @llvm.amdgcn.buffer.atomic.xor(i32, <4 x i32>, i32, i32, i1) #0
 declare i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32, i32, <4 x i32>, i32, i32, i1) #0
 
 attributes #0 = { nounwind }