[X86] Fix PR23155 by turning on X86FixupBWInsts by default

[kbsmith1]

Summary

This fixes PR23155 by turning on the X86FixupBWInst optimization by default,
and modifies the few tests that are affected by this. The X86FixupBWInst optimization
already has its unit tests, which were checked in with its initial commit.

[spatel]

LGTM.
Have you measured any other perf diffs using this pass besides the case in PR23155?

[kbsmith1]

Yes, I have run perf results locally on a number of different kinds of boxes. As stated this does generate exactly the code desired
for PR23155 (modulo the alignment differences noted as having some performance effect in that PR).

Some highlights
+8% on EEMBC/viterb (this was what motivated PR23155)
+3% on spec2000 parser
+2% on spec2000 twolf
+3% on EEMBC/ip_reassemblyIT,tcpbulk,tcpmixed
+2% on EEMBC/qos,natIT

a couple of minor degrades as well
-3 on EEMBC/puwmod01
-2 on coremark/zip-test
-2 on spec2006/libquantum -O2,but +1% -O2 +Haswell specific cpu tuning flags.

So, generally this doesn't make a big difference on benchmarks, but is more positive than negative.

lib/Target/X86/X86FixupBWInsts.cpp

 #define DEBUG_TYPE "x86-fixup-bw-insts"
 
 // Option to allow this optimization pass to have fine-grained control.
 // This is turned off by default so as not to affect a large number of
 // existing lit tests.
 static cl::opt<bool>
     FixupBWInsts("fixup-byte-word-insts",
                  cl::desc("Change byte and word instructions to larger sizes"),
-                 cl::init(false), cl::Hidden);
+                 cl::init(true), cl::Hidden);
 
 namespace {
 class FixupBWInstPass : public MachineFunctionPass {
   static char ID;
 
   const char *getPassName() const override {
     return "X86 Byte/Word Instruction Fixup";
   }

test/CodeGen/X86/anyext.ll

; X64-NEXT:    retq
   %s = zext i8 %r to i32
   %t = and i32 %s, 1
   ret i32 %t
 }
 
 define i32 @bar(i32 %p, i16 zeroext %x) nounwind {
 ; X32-LABEL: bar:
 ; X32:       # BB#0:
-; X32-NEXT:    movw {{[0-9]+}}(%esp), %ax
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    xorl %edx, %edx
 ; X32-NEXT:    divw {{[0-9]+}}(%esp)
 ; X32-NEXT:    andl $1, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: bar:
 ; X64:       # BB#0:
 ; X64-NEXT:    xorl %edx, %edx

test/CodeGen/X86/avx512bw-intrinsics.ll

 ; AVX512BW-NEXT:    vpbroadcastw %di, %zmm1 {%k1} {z}
 ; AVX512BW-NEXT:    vpbroadcastw %di, %zmm2
 ; AVX512BW-NEXT:    vpaddw %zmm0, %zmm2, %zmm0
 ; AVX512BW-NEXT:    vpaddw %zmm0, %zmm1, %zmm0
 ; AVX512BW-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: test_int_x86_avx512_mask_pbroadcast_w_gpr_512:
 ; AVX512F-32:       # BB#0:
-; AVX512F-32-NEXT:    movw {{[0-9]+}}(%esp), %ax
+; AVX512F-32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k1
 ; AVX512F-32-NEXT:    vpbroadcastw %ax, %zmm0 {%k1}
 ; AVX512F-32-NEXT:    vpbroadcastw %ax, %zmm1 {%k1} {z}
 ; AVX512F-32-NEXT:    vpbroadcastw %ax, %zmm2
 ; AVX512F-32-NEXT:    vpaddw %zmm0, %zmm2, %zmm0
 ; AVX512F-32-NEXT:    vpaddw %zmm0, %zmm1, %zmm0
 ; AVX512F-32-NEXT:    retl
   %res = call <32 x i16> @llvm.x86.avx512.mask.pbroadcast.w.gpr.512(i16 %x0, <32 x i16> %x1, i32 -1)
   %res1 = call <32 x i16> @llvm.x86.avx512.mask.pbroadcast.w.gpr.512(i16 %x0, <32 x i16> %x1, i32 %mask)
   %res2 = call <32 x i16> @llvm.x86.avx512.mask.pbroadcast.w.gpr.512(i16 %x0, <32 x i16> zeroinitializer, i32 %mask)
   %res3 = add <32 x i16> %res, %res1
   %res4 = add <32 x i16> %res2, %res3
   ret <32 x i16> %res4
 }

test/CodeGen/X86/merge-store-partially-alias-loads.ll

 ; REQUIRES: asserts
 ; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck -check-prefix=X86 %s
 ; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -debug-only=isel < %s 2>&1 | FileCheck -check-prefix=DBGDAG %s
 
 ; It's OK to merge the load / store of the first 2 components, but
 ; they must not be placed on the same chain after merging.
 
 ; X86-LABEL: {{^}}merge_store_partial_overlap_load:
-; X86-DAG: movw ([[BASEREG:%[a-z]+]]), [[LO2:%[a-z]+]]
+; X86-DAG: movzwl ([[BASEREG:%[a-z]+]]), %e[[LO2:[a-z]+]]
 ; X86-DAG: movb 2([[BASEREG]]), [[HI1:%[a-z]+]]
 
-; X86-NEXT: movw [[LO2]], 1([[BASEREG]])
+; X86-NEXT: movw %[[LO2]], 1([[BASEREG]])
 ; X86-NEXT: movb [[HI1]], 3([[BASEREG]])
 ; X86-NEXT: retq
 
 ; DBGDAG-LABEL: Optimized lowered selection DAG: BB#0 'merge_store_partial_overlap_load:'
 ; DBGDAG: [[ENTRYTOKEN:t[0-9]+]]: ch = EntryToken
 ; DBGDAG-DAG: [[BASEPTR:t[0-9]+]]: i64,ch = CopyFromReg [[ENTRYTOKEN]],
 ; DBGDAG-DAG: [[ADDPTR:t[0-9]+]]: i64 = add [[BASEPTR]], Constant:i64<2>