[mips] Trivial corrections to range checked immediates.

[dsanders]

Summary

SYNC has a 5-bit unsigned immediate.
Move MIPS16-specific pcrel16 operand to Mips16 files.

Depends on D18439

[vkalintiris]

LGTM.

lib/Target/Mips/MicroMips32r6InstrInfo.td

class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
   bit hasSideEffects = 0;
   bit isReMaterializable = 1;
   InstrItinClass Itinerary = II_LUI;
   Format Form = FrmI;
 }
 
 class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
   dag OutOperandList = (outs);
-  dag InOperandList = (ins i32imm:$stype);
+  dag InOperandList = (ins uimm5:$stype);
   string AsmString = !strconcat("sync", "\t$stype");
-  list<dag> Pattern = [(MipsSync imm:$stype)];
+  list<dag> Pattern = [(MipsSync immZExt5:$stype)];
   InstrItinClass Itinerary = NoItinerary;
   bit HasSideEffects = 1;
 }
 
 class SYNCI_MMR6_DESC : SYNCI_FT<"synci"> {
   let DecoderMethod = "DecodeSynciR6";
 }
 

lib/Target/Mips/Mips16InstrInfo.td

 }
 
 def mem16_ea : Operand<i32> {
   let PrintMethod = "printMemOperandEA";
   let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
   let EncoderMethod = "getMemEncoding";
 }
 
+def pcrel16 : Operand<i32>;
+
 //
 // I-type instruction format
 //
 // this is only used by bimm. the actual assembly value is a 12 bit signed
 // number
 //
 class FI16_ins<bits<5> op, string asmstr, InstrItinClass itin>:
   FI16<op, (outs), (ins brtarget:$imm16),

lib/Target/Mips/MipsInstrInfo.td

 }
 
 // This is almost the same as a uimm7 but 0x7f is interpreted as -1.
 def li16_imm : Operand<i32> {
   let DecoderMethod = "DecodeLi16Imm";
   let ParserMatchClass = ConstantUImm7Sub1AsmOperandClass;
 }
 
-
-def pcrel16      : Operand<i32> {
-}
-
 def MipsMemAsmOperand : AsmOperandClass {
   let Name = "Mem";
   let ParserMethod = "parseMemOperand";
 }
 
 def MipsMemSimm9AsmOperand : AsmOperandClass {
   let Name = "MemOffsetSimm9";
   let SuperClasses = [MipsMemAsmOperand];

 // Interrupts
 class DEI_FT<string opstr, RegisterOperand RO> :
   InstSE<(outs RO:$rt), (ins),
          !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
 
 // Sync
 let hasSideEffects = 1 in
 class SYNC_FT<string opstr> :
-  InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
-         NoItinerary, FrmOther, opstr>;
+  InstSE<(outs), (ins uimm5:$stype), "sync $stype",
+         [(MipsSync immZExt5:$stype)], NoItinerary, FrmOther, opstr>;
 
 class SYNCI_FT<string opstr> :
   InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
          NoItinerary, FrmOther, opstr> {
   let hasSideEffects = 1;
   let DecoderMethod = "DecodeSyncI";
 }
 
let DecoderNamespace = "COP3_" in {
   def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
   def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
              ISA_MIPS2;
   def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
              ISA_MIPS2;
 }
 }
 
-def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
+def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM,
+           ISA_MIPS32;
 def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
 
 let AdditionalPredicates = [NotInMicroMips] in {
   def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10>, TEQ_FM<0x34>, ISA_MIPS2;
   def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10>, TEQ_FM<0x30>, ISA_MIPS2;
   def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10>, TEQ_FM<0x31>, ISA_MIPS2;
   def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm10>, TEQ_FM<0x32>, ISA_MIPS2;
   def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10>, TEQ_FM<0x33>, ISA_MIPS2;

test/MC/Mips/micromips/invalid.s

# RUN: FileCheck %s < %t1
   sdbbp16 -1          # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
   sdbbp16 16          # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
   sll $2, $3, -1      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   sll $2, $3, 32      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   sra $2, $3, -1      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   sra $2, $3, 32      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   srl $2, $3, -1      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   srl $2, $3, 32      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sync -1             # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
+  sync 32             # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
   swe $2, -513($gp)   # CHECK: :[[@LINE]]:11: error: expected memory with $gp and 9-bit signed offset
   swe $2, 512($gp)    # CHECK: :[[@LINE]]:11: error: expected memory with $gp and 9-bit signed offset

test/MC/Mips/micromips32r6/invalid.s

# RUN: FileCheck %s < %t1
   sb16 $9, 4($16)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sb16 $3, 64($16)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   sb16 $16, 4($16)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sb16 $7, 4($9)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sh16  $9, 8($17)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sh16  $4, 68($17)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   sh16  $16, 8($17)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sh16  $7, 8($9)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sync -1                  # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
+  sync 32                  # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
   sw16  $9, 4($17)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sw16  $4, 64($17)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   sw16  $16, 4($17)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sw16  $7, 4($10)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $5, $6, $ra, 8($sp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
   swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
   swm16 $16-$25, $ra, 8($sp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
   swm16 $16, 8($sp)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/mips32r2/invalid.s

# RUN: FileCheck %s < %t1
         sdbbp -1             # CHECK: :[[@LINE]]:15: error: expected 20-bit unsigned immediate
         sdbbp 1048576        # CHECK: :[[@LINE]]:15: error: expected 20-bit unsigned immediate
         sll $2, $3, -1       # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
         sll $2, $3, 32       # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
         srl $2, $3, -1       # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
         srl $2, $3, 32       # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
         sra $2, $3, -1       # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
         sra $2, $3, 32       # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
+        sync -1              # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
+        sync 32              # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         syscall -1           # CHECK: :[[@LINE]]:17: error: expected 20-bit unsigned immediate
         syscall 1048576      # CHECK: :[[@LINE]]:17: error: expected 20-bit unsigned immediate
         rotr $2, $3, -1      # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
         rotr $2, $3, 32      # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
         xori $2, $3, -1      # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
         xori $2, $3, 65536   # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate

test/MC/Mips/mips32r6/invalid.s

local_label:
         mtc2  $4, $3, -1     # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         mtc2  $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         mfc0  $4, $3, -1     # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         mfc0  $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         mfc2  $4, $3, -1     # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         mfc2  $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         sdc2 $20, -1025($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         sdc2 $20, 1024($s2)  # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
+        sync -1              # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
+        sync 32              # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate